Advanced Process Technologies - Part 3: FinFET Layout

This is part 3 of my lecture on Advanced Process Technologies.

In this lecture, I introduce advanced process technologies based on FinFET (Tri-gate) structures. In the lecture, I start with the motivation for the move to the "third-dimension" and then overview the primary mechanisms for fabricating a deeply scaled (22nm and below) FinFET device in comparison with traditional planar device fabrication. This leads to the perspective of FinFETs from a designers point of view, taking a look at the features of these new devices and process nodes and focusing on transistor layout, layout-dependent effects (LDEs) and device parasitics. I wrap up my talk with a look to the near-future with the current trends of gate-all-around (GAA) nano-sheet (nano-ribbon) devices and buried power rails.

Many thanks to Alvin Loke for his great tutorials on these subjects in recent years and Or Nahum, who taught me a lot about the process aspects of deep nanoscale fabrication.

All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[jia-huacheng]

So far, this is one of the highest-quality courses I have ever seen for FinFET. Really happy to find your video. We are eager to learn!! Please feed us more :)

[sagarkore]

Sir Classic Explanation of layout. Thank you so much for your hard work and effort .. to make things so simple to understand.

[uglykevin]

Sir, thanks a lot, I'm currently working at advanced packaging area. Your video helps me understand FEOL a lot!

[ctnrb]

Thank you so much. As a PD engineer this helped me a lot in understanding FINFETs. The graphics, the explanation, the flow of information was just perfect

[anuragharidasu]

Thank you so much the detailed explanation

[쯔무쯔무]

Thank you for the good lecture. It was very helpful.

Could you tell me about the question below?

1. What is the purpose of using the "gate cut layer" in the 14nm process? In my understanding, the gate cut layer also plays a role in separating the gate area of TR from other TRs.

You said that dummy gate pc also separates the active region, but I would like to know the difference.

2. When layout, is the big difference between 14nm and 10nm about "COAG"? (deleted, I'm sorry I asked you a question)

3. Could you make a detailed lecture on layout of GAA? I haven't experienced this process yet, so I'm very interested.

Have a nice day :)

[DM]

Well done. In 9:16 what is meant by 'Here we have VG which is a *coag* '?