filmov
tv
Enhancing OFI for Invoking Acceleration Capabilities on an Integrated Networking/Accelerator FPGA...
Показать описание
Enhancing OFI for Invoking Acceleration Capabilities on an Integrated Networking/Accelerator FPGA Platform (COPA)
Venkata Krishnan, Intel, Corp.
Venkata Krishnan focuses on various aspects of microprocessor architecture, accelerators and networking. He holds a B.Tech from IIT Madras and a PhD from University of Illinois at Urbana-Champaign in Computer Science. Prior to joining Intel, he has held other positions that include CTO of Dolphin Interconnect, research scientist at DE Shaw research and fellow at AMD.
FPGAs provide advanced capabilities that traditional processors offer and additionally offer hardware acceleration capabilities. Unfortunately, lack of infrastructure has relegated FPGAs to being second-class citizens rather than being autonomous nodes in a cluster. This stands in the way of a truly distributed/heterogenous computing model. The Configurable network Protocol Accelerator (COPA) project addresses this challenge by providing a framework that integrates communication with computation on an FPGA platform. COPA has been implemented on a Stratix10 FPGA (SOC and non-SOC) and a PCIe Stratix10 attached to a Xeon host. Multiple FPGAs attach to a standard 100GigE switching network with the ability to mix-and-match the FPGA type that attaches to the network. A software stack that exposes the acceleration and networking capabilities to the application is a key feature of COPA. Obviously, extending a network API to include acceleration support is easier than extending a standard acceleration API to support network communication. Hence, COPA software supports OFI with extensions for exposing the various acceleration modes to the application. This presentation will provide a short overview of COPA and the different acceleration modes that it supports along with the OFI extensions in place to invoke them.
Venkata Krishnan, Intel, Corp.
Venkata Krishnan focuses on various aspects of microprocessor architecture, accelerators and networking. He holds a B.Tech from IIT Madras and a PhD from University of Illinois at Urbana-Champaign in Computer Science. Prior to joining Intel, he has held other positions that include CTO of Dolphin Interconnect, research scientist at DE Shaw research and fellow at AMD.
FPGAs provide advanced capabilities that traditional processors offer and additionally offer hardware acceleration capabilities. Unfortunately, lack of infrastructure has relegated FPGAs to being second-class citizens rather than being autonomous nodes in a cluster. This stands in the way of a truly distributed/heterogenous computing model. The Configurable network Protocol Accelerator (COPA) project addresses this challenge by providing a framework that integrates communication with computation on an FPGA platform. COPA has been implemented on a Stratix10 FPGA (SOC and non-SOC) and a PCIe Stratix10 attached to a Xeon host. Multiple FPGAs attach to a standard 100GigE switching network with the ability to mix-and-match the FPGA type that attaches to the network. A software stack that exposes the acceleration and networking capabilities to the application is a key feature of COPA. Obviously, extending a network API to include acceleration support is easier than extending a standard acceleration API to support network communication. Hence, COPA software supports OFI with extensions for exposing the various acceleration modes to the application. This presentation will provide a short overview of COPA and the different acceleration modes that it supports along with the OFI extensions in place to invoke them.