How To Measure Low Impedance With An Affordable VNA And Using Free Tools

Explained how to measure impedance. Thank you very much Adinath Phene

Links:

Chapters:
00:00 What is this video about
01:05 Why we would like to measure PDN
10:47 1-Port vs 2-Port measurement
13:32 Setup and calibration
20:19 Measuring a resistor with VNA
25:25 Importing measurement to Qucs
30:35 Measurement vs Simulation
34:31 Impedance of different resistors
41:06 Impedance of a solder blob
44:00 The VNA we used - SDR VNA (SDR Kits)
46:25 Impedance measurement and simulation of a capacitor
50:16 Impedance of a capacitor with different VIA connections
55:52 Impedance of X2Y capacitor vs MLCC capacitor
59:22 Impedance of Electrolytic vs Tantalum vs MLCC capacitors
1:04:03 What to try after this video

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Would you like to support me? It's simple:

It is much appreciated. Thank you,
- Robert

[wbond]

Interesting video. thanks for making that available to the general public. I wanted to mention that the SDR VNA software allows plotting of the impedance formula within the program... Again thanks..

[ats]

Great video! When Adinath didn't completely agree with your simplifications, he would go silent, which was also instructive! 😀

[gsuberland]

Another interesting thing to look at is AVX's interdigitated capacitors (IDCs), which come in multi-pin packages similar to resistor arrays. They are still a single capacitor internally, but by connecting the pairs of terminals in opposite polarity you create opposing current loops that reduce inductance. They do make layout a little trickier in dense areas since you need to be able to fit vias nearby in opposing patterns, but often your BGA/LGA packages have alternating GND/Vxx pads anyway for referencing when they have high power integrity requirements, so direct in-pad connection is often possible there.

[kxo]

It would be interesting to see the difference between <=0201 package size mlcc vs 0402 x2y cap at same capacitance. Furthermore I would like to know the difference in esl when using 2 super close vias vs multiple vias. I think the esl should be lower than inpad vias because the distance is shorter.

[miroslawkaras]

For port isolatio or noise floor you shoul terminate both ports withh 500 ohms termination. When you calibrate you shoul not connect you standards (open, short, load thru adapter), they should be connected direcly to thend of the cable to avoid any phase diffrence.

[fabioposser]

Hi Robert, do you have a video teaching how to choose the profile for the IC? Because I have tools like siwave, but I have doubts how to select the desired impedance for the IC and also how to know the output impedance characteristics of a buck converter for example.

[tianheyun-ez]

The PCB board of the test fixture is not embedded. How to eliminate the influence of that test board?

[samihawasli]

Very good presentation, but can I ask? Isn't it bad your S-Parameters were outside the smith chart for your passive resistor? Seems concerning since we then used those S-paramtesr to calculate Zdut

[veni]

Great video! Didn't get it: what's the difference between shorted trace and blob of solder?

[MrThoriam]

Can somebody explain me the equation how he get impedance from insertion loss? Im a little bit confused. Btw great video

[moseschan]

why not nanoVNA ? This device seems really slow and has low bandwidth