PCIe Architecture : PCIe Enumeration

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This video explains the following in PCIe Architecture
Basic concepts and PCIe terminology
PCIe enumeration concept
Configuration registers
Configuration Access mechanism
Extended configuration Access Mechanism
Enumeration process

PCIe

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Some corrections
1. Used the word host bridge instead of root complex. Root complex connects cpu to PCIe devices discussed in previous video also.
2. In enumeration process used bus0 dev0 function 0 instead of bus0 dev1/dev3/dev4 fun 0.

pcie

Hi, Your illustration and zeal to make people understand is outstanding. i really like the content and the way you try to make people understand each and every aspect of the topic you cover. Keep up the good work! It would be great to get to know you better..

utkarshbhatnagar

During Enumeration, CPU do the depth first strategy to find the End Points. during the depth CPU configures the each end point? or it only discovers the PCIe endpoints location, later will do the configuration of each points?

RajuRajuRaju

sir your teachining excelent
sir i kindly request to you can you enplane link initialization we are waiting for your teaching please sir that topic is very need for us.

nagaraju-jorx

Please add NVMe protocol Architecture. Working with PCIe and NVMe

shaminpm

I have doubt like after primary secondary and subordinate when bus device and function come into picture and when we will represent function with 1 and when will device numbers change in one branch device number is completely zero in other branch device number changes

maddalasaibhaskar

sir, ...pls come with preparation and clr voice

prashant_daharwal

set playback speed to 1.25x. Your Welcome

AbdulRehman-jnwe

why you are too slow while speaking ...also not speaking clearly ....contents are good, but your style ruins the fun part of video

realtime

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