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PCI Express Physical Layer
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PCI Express Physical Layer
An overview of PCI Express Physical Layer Technology
- Part 1: Electrical
by John Gulbrandsen, Consultant, June 2016
I will in this presentation explain:
The main problems with the legacy PCI bus that prompted the development of the new PCI Express architecture.
An overview of the physical layer (hardware aspects) of the PCI Express bus and how it differs from PCI.
Future presentations will cover higher protocol layers and the associated software features.
Physical Layer Overview
PCIe Physical Layer - Slot Connector
PCIe Physical Layer – links and lanes
PCIe Physical Layer – Differential signaling
PCIe Physical Layer – Pre-emphasis
PCIe Physical Layer – Data Scrambling
PCIe Physical Layer – 8b/10b Encoding
PCIe Physical Layer – Embedded Clock
PCIe Physical Layer – Clock Recovery
PCIe Physical Layer – Data Striping
PCIe Physical Layer - Bandwidth
PCIe Physical Layer – Link Training
PCIe Physical Layer – Signal Integrity
PCIe Physical Layer – Keep Channel Impedance 50 ohm (SE) or 100 ohm (Diff.)
PCIe Physical Layer – keep PCB traces short
PCIe Physical Layer – keep PCB traces short
PCIe Physical Layer – Length Matching
PCIe Physical Layer – Length Matching
PCIe Physical Layer – SERDES example
PCIe Physical Layer – SERDES TX – Step 1/3
PCIe Physical Layer – SERDES TX – Step 2/3
PCIe Physical Layer – SERDES TX – Step 3/3
PCIe Physical Layer – SERDES RX – Step 1/5
PCIe Physical Layer – SERDES RX – Step 2/5
PCIe Physical Layer – SERDES RX – Step 3/5
PCIe Physical Layer – SERDES RX – Step 4/5
PCIe Physical Layer – SERDES RX – Step 5/5
PCIe Physical Layer – Analog Lab Instruments
PCIe Physical Layer – Digital Lab Instruments
PCIe Physical Layer – Books
About Summit Soft Consulting & John Gulbrandsen, Consultant
Company HistorySummit Soft Consulting was founded to offer expert consulting services in device driver and electronics peripheral device design. Over the 20
years we have been in the electronics and software engineering fields, we have had extensive experience with microcontrollers, digital and analog electronics, Windows x86/x64 software and device driver implementation, high-speed board design, signal and power integrity, advanced FPGA digital designs,
USB and PCI Express Protocol Analyzer designs and much more.
Summit Soft Consulting is comprised of a team of consultants, each with complementary or overlapping skills related to Windows Systems Programming and
Advanced Electronics Design. In addition, we work with a growing network of individual consultants across United States, which allows us to provide specialty
niche expertise that, perhaps, may not be readily available in-house. The end benefit for you, our client, is that you will work with our competent and
experienced team that safely will bring your project to completion within set cost and time budgets. We are located in Aliso Viejo, Orange County, Southern
California, mid-way between Los Angeles and San Diego.
An overview of PCI Express Physical Layer Technology
- Part 1: Electrical
by John Gulbrandsen, Consultant, June 2016
I will in this presentation explain:
The main problems with the legacy PCI bus that prompted the development of the new PCI Express architecture.
An overview of the physical layer (hardware aspects) of the PCI Express bus and how it differs from PCI.
Future presentations will cover higher protocol layers and the associated software features.
Physical Layer Overview
PCIe Physical Layer - Slot Connector
PCIe Physical Layer – links and lanes
PCIe Physical Layer – Differential signaling
PCIe Physical Layer – Pre-emphasis
PCIe Physical Layer – Data Scrambling
PCIe Physical Layer – 8b/10b Encoding
PCIe Physical Layer – Embedded Clock
PCIe Physical Layer – Clock Recovery
PCIe Physical Layer – Data Striping
PCIe Physical Layer - Bandwidth
PCIe Physical Layer – Link Training
PCIe Physical Layer – Signal Integrity
PCIe Physical Layer – Keep Channel Impedance 50 ohm (SE) or 100 ohm (Diff.)
PCIe Physical Layer – keep PCB traces short
PCIe Physical Layer – keep PCB traces short
PCIe Physical Layer – Length Matching
PCIe Physical Layer – Length Matching
PCIe Physical Layer – SERDES example
PCIe Physical Layer – SERDES TX – Step 1/3
PCIe Physical Layer – SERDES TX – Step 2/3
PCIe Physical Layer – SERDES TX – Step 3/3
PCIe Physical Layer – SERDES RX – Step 1/5
PCIe Physical Layer – SERDES RX – Step 2/5
PCIe Physical Layer – SERDES RX – Step 3/5
PCIe Physical Layer – SERDES RX – Step 4/5
PCIe Physical Layer – SERDES RX – Step 5/5
PCIe Physical Layer – Analog Lab Instruments
PCIe Physical Layer – Digital Lab Instruments
PCIe Physical Layer – Books
About Summit Soft Consulting & John Gulbrandsen, Consultant
Company HistorySummit Soft Consulting was founded to offer expert consulting services in device driver and electronics peripheral device design. Over the 20
years we have been in the electronics and software engineering fields, we have had extensive experience with microcontrollers, digital and analog electronics, Windows x86/x64 software and device driver implementation, high-speed board design, signal and power integrity, advanced FPGA digital designs,
USB and PCI Express Protocol Analyzer designs and much more.
Summit Soft Consulting is comprised of a team of consultants, each with complementary or overlapping skills related to Windows Systems Programming and
Advanced Electronics Design. In addition, we work with a growing network of individual consultants across United States, which allows us to provide specialty
niche expertise that, perhaps, may not be readily available in-house. The end benefit for you, our client, is that you will work with our competent and
experienced team that safely will bring your project to completion within set cost and time budgets. We are located in Aliso Viejo, Orange County, Southern
California, mid-way between Los Angeles and San Diego.
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