Crazy FPGA - One Million Bits Adder - Сумматор на миллион бит

Hey, FPGA!
This is a CRAZY FPGA series with abstract ideas. This episode contains implementation of One Million Bits Adder
--
--
Русскоязычное FPGA комьюнити:
--
--

[ДмитрийГладченко-рб]

Ребята, вы маньяки)) продолжайте в том же духе!!

[inkgloria]

Интересно, а если использовать DSP модули, сколько еще бит влезло бы?

[coding_vlsi_vietnam]

it 's so fast. Nothing to learn here

[MegaVolt_ex]

И какова рабочая частота этого монстра?

[alexplishkin]

Привет. Я новичек. Подскажите с чего начать? Спасибо!

[edwardfisher]

I think this is deeply unrepresentative. No timing analysis and no clock meaning the more bits the slower it is. Far better to show robust design as #bits increases using pipelining, replication and changes to the base adder structure and carry lookahead etc.

I take it this is utterly slow and power hungry.

How would you design this is you needed to achieve this at 100MHz? How would you partition and retime it?

How would you achieve large number of bit additions if unable to switch to larger FPGA?

Such lazy design will not be viewed well in industry.