Designing a Lead Compensator with Bode Plot

This video walks through a phase lead compensator example using the Bode Plot method.

Errata:
Around 7:00 I added an additional '+1' in the denominator of the Ess equation. The denominator should be 0.2s^2 + s + k.

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[BrianBDouglas]

Thanks for the comment! My background is dynamics and controls in aerospace engineering from university. But the majority of my working experience is with satellite guidance, navigation, and control.

[tomersvirsky]

120k views and I'm responsible for at least a half of them

[cWeeks]

You're an amazing teacher. And video editor. The fact that I don't have to wait to see you write something down, and you're writing it down as you're saying it, along with one fluid document and nice colors, makes this series amazing. Thank you so much

[jjaya]

i think you meant to say +6dB:) Awesome videos BTW.

[randywells]

at 6:57 you have 0.2s^2 + s + K + 1 in the denominator. When I do the math the 1 is not there. Am I doing something wrong?

[BrianBDouglas]

Hello again! Yes you are correct it is obvious from the graph that the DC gain is +6dB :-) Thanks for pointing that out. I'll add an annotation to correct it. And you are right that you wouldn't have a gain crossover frequency in your case. And that means that your system (assuming this was a Bode plot for an open loop system that you were planning on closing) would have infinite phase margin! Or no matter how much delay the system had it would still be stable.

[enk]

Brian, I am a ME grad student with one of my concentrations focused on controls. I just want to say without your videos I would not fully understand the concepts that are being fully covered in class. Thank you very much you are awesome!

[nicoletteforhan]

How did you get wm to equal 22.2?? Thank you for all you help! I love your videos.

[kjiings]

Hey Brian. At 6:59, shouldn't the equation be (0.2s^2 + 1)/(0.2s^2+s+k)? how comes there is an additional "+1" in the denominator?

[Momomomomomomo]

Oh my god could you please teach my university professor how to teach the course? You are just amazing

[Dany_B_Good]

Hi! Thank you so much for this video. I still don't get how you were able to calculate wm, did you just chose it? Does anybody know ho he did it? Thanks in advance.

[BrianBDouglas]

You can use the command margin(sys) in the command window to bring up a Bode plot with the gain and phase margins in the title. Another way to show margins is to type bode(sys) and right click on the graph, -> Characteristics, -> All Stability Margins.

[kshitijbhatnagar]

at 12:10 the value of wm is selected as 22.2 rad/sec how it is selected and second thing how is this table over a2 id built

[BrianBDouglas]

then the concept of bandwidth doesn't make much sense. Also, once thing that drives me crazy is that the term bandwidth is used in so many applications that it's hard to keep track of the meaning one person is using versus another. Therefore, I should have just said the -3dB gain frequency and left it at that. And if there is no -3dB gain frequency then it doesn't exist.

[surajdamodaran]

You're an amazing thank you for sharing the videos....I have a doubt....K > 50 right?

[purbabiswas]

How in the denominator you got 0.2s^2+s+k+1? Shouldn't it be 0.2s^2+s+k.

[BrianBDouglas]

Also, the -3dB gain, which can be called the bandwidth of a system, is the frequency at which the output signal is sqrt(2)/2 times smaller than the input. This is traditionally thought of the as the frequency above which the system effectively attenuates the signal so much that it doesn't pass it through. Of course there is a little attenuation at lower frequencies and some passing at higher frequencies but it gives a good measure. So if your signal cut all gains in half at all frequencies ...

[BrianBDouglas]

There's a subtle difference between the two ways I presented the data and so I can see now that it is very confusing. In this video I am talking about the steady state ERROR to a ramp input. If you have a type 0 system with a ramp input the final ERROR in the system will be inf, which means your system does a poor job of tracking that input. In the other video I was talking about the steady state value of the OUTPUT, not the error. In a type 0 stable system the final output is 0 to an impulse.

[mehmetmucahitdonmez]

Sir i think there is a mistake at 6:52. There should't be +1 at the denumerator side

[arminjafari]

Dear Brian, tnx for the video, as a question:
Is this problem (we cannot add more than 55 deg of Phase Margin using lead compensator, otherwise the components become unrealistic and big) also includes digital implementation? Because in digital control, we do not use capacitors and opamps anymore, and therefore the implementation of phase margins larger than 55 might be easy.... what is your opinion about this?