Timescale in Verilog | System Verilog timescale | Compiler Directive `timescale | Verilog Time delay

In this Video, I have explained about What is Verilog/System Verilog Compiler Directive `timescale. How these `timescale determine the delay units specified in the design. How `timescale will be used to calculate delay units in design.

Keywords:
Timescale in Verilog, Timescale in System Verilog, Verilog Time Precision, Verilog Time Unit, Verilog compiler directive, Verilog `timescale directive, System Verilog Time Precision, System Verilog Time Unit, System Verilog compiler directive, System Verilog `timescale directive, Verilog delay units, System Verilog delay Units, Electronicspedia, Best VLSI channel, VLSI Youtube channel, VLSI Design lectures, VLSI course, Verilog Tutorials, Basics of Verilog, Basics of System Verilog, Verilog coding, VLSI Design,

#verilog #timescale #systemverilog

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[preetamdewangansirclasses]

sir $realtime will equal to 15.6 ns only. $time will be equal to 16ns.

[rahulbhadoria_]

Thank you Sir for this simple explanation 👏👏🤗

[Platica.Vasile]

Thank you for the quick video, but for a more thoroughly you should corelate this with a timer to see exactly how the timescale affects the program.

[nenadmilutinovic]

Hello Sir, what will 15.5 be rounded off to? 16 or 15?
Thank you in advance!

[RanjanSingh-pmze]

Sir if possible then please make a playlist on system verilog. Because there is no one at YouTube who is teaching like you. Everyone is using just ppt for teaching purpose. Even there are many famous institute they are just using ppt.

[preetamdewangansirclasses]

sir kindly extend this discussion considering ps as a precision