Learn VERILOG for VLSI Placements for FREE | whyRD

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You need just 30 days to learn the language of VLSI design, a must for all front-end digital profile jobs and also a must-know domain for all VLSI engineers.

About myself: Hi, I am Rajdeep Mazumder, I did my MTech from IIT Delhi in Radiofrequency design and technology. Presently I am working as a hardware engineer with Intel. I am an engineering enthusiast and daily meditator and want to build hardcore engineering teaching as my profession.
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Time Stamps
00:00. Is 30 days enough for Verilog ?
00:39 Video contents
01:21 Why Verilog is different?
02:10 Day 1-5 Revision
04:45 What does learning Verilog mean?
05:52 Day 6-16 Verilog Learning Resources
07:04 Day 17-30 Practise Verilog (with Demo)
13:50 Previous year VLSI Interview Questions
14:57 Bonus Resources




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#whyRD #VLSI #verilog

[abhinandhanvuppala]

Bro i am currently pursuing 3rd year my request is to do a video how we can get internships in our core domain so which improves our work exposure

[yobuddy]

brother, you are truly gem for me
i was searching for these kind of information for so long but i found it now.
million thanks to u brother❤

[DivyaSree-]

Such a nice content brother .iam a 2024 passed out btech so i want to go with VLSI So i wiil start by u r guidance thank you brother and one more please provide the notes if u havee

[yashwantht]

@whyRD please re-upload this video again we are facing the issues. Great content always willing to see the video and follow the instruction by you.

[jagatpatiraiguru]

Thank You WhyRD ...very nice way you have described the directions to learn Verilog ...Thanks for sharing ..Keep It up

[divyanityagi]

Sir one of my friend have done btech in ECE in 2018. Since then he was preparing for UPSC but couldn't clear.Now he want to join VLSI industry, well his education gap has any effects.

[coding_vlsi_vietnam]

Verilog, sv, vhdl are interesting but VLSI is not popular as python, javascript so if you buid a youtube channel about vlsi i think that it 's difficult to approach audicine. Anyway your channel is very helpfull 😁

[sebastinraja]

Hi Raj, Please make a video for post silicon validation engineer role and interview preparation strategies.

[marwanal-yoonus]

Dear Sir
Thank you very much for this helpful video
Please, I try to write the following Verilog code in Vivado, the synthesis process is OK but when I want to implement it an error signal appear !!

module Tog_not (hsync, EOL, q);
input hsync, EOL;
output reg q;
always @ (posedge hsync)
begin
q<=1'b0;
end
always @ (posedge EOL)
begin
q<=1'b1;
end
endmodule

Could you help me for that? Thank you again.

[raspberrypi]

Sir, will you recommend studying from book Verilog HDL: A Guide to Digital Design and Synthesis by Samir Palnitkar?

[zaidrehman]

VHDL or verilog which I should go for as a beginner

[kadajaganmohanachari]

can you please tell the best platform for learning digital electronics

[rtk]

RD sir, please tell me the roadmap to learn VHDL

[Deepak-ygil]

Hello Rajdeep Iam, confusing write now, for choosing carrier in IT or Vlsi

[rakeshmahapatra]

Sir, kindly share Where to learn system verilog? Any videos reverence

[Gurumurthy]

Hello sir! It was a good informative video. I have one doubt, will freshers get refferal by employees in analog vlsi domain

[anilrella]

Bayya I want ` time scale concept when 1ns/1ps why we multiply that value 1000

[PrashanthsVlog]

What is the website your using for writing code? Please anybody answer this

[SoubhagyaM-lz]

Currently i am doing mtech in vlsi and embedded system. Can u tell me other than academic wt i can do to start my career in vlsi and embedded system

[raishydermirza]

Hi sir...
Your content is just amazing as you...
Sir I'm present in 3rd year I want to do internship in VLSI domain after few months so sir pls suggest any industries to do internship in offline... 🙏