Introduction to Verilog HDL using Free Software Icarus, GTKWave, and VS Code

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00:03 What is Hardware Description Language?
00:23 Advantage of Textual Form Design
01:03 Altera HDL or AHDL
01:19 Just-Another HDL (JHDL)
01:33 VHSIC HDL (VHDL)
01:56 Meaning of VHSIC
02:30 Verilog
02:13 SystemVerilog
02:36 Test Bench
02:59 Logic Synthesis
03:06 Netlist
03:13 Verilog Modeling Styles
03:19 Gate-level Modeling
03:26 DataFlow Modeling
03:36 Behavioural Modeling
03:53 Verilog is case-sensitive just like C
04:06 White spaces, tabs, new lines are ignored
04:13 Keywords are lowercase
04:26 How to name a variable
04:36 System tasks or function starts with dollar sign
04:43 One line and multi-line comments
05:06 note on the old and new version of the syntax
05:13 module endmodule keyword pair
05:29 module name
05:33 port list
05:59 input and output keywords
06:19 Statements are terminated by semicolon
06:33 Icarus is Free and can be used offline
06:49 How to install iverilog
07:33 How to install Icarus for Windows
10:03 Where the verilog bin libraries or executables?
10:23 How to update PATH environment variables
11:46 How to check if iverilog is installed
11:56 How to view iverilog version
12:23 How to install Visual Studio Code Text Editor
14:06 How to customize or configure VS Code for Verilog
14:19 Verilog HDL extension
15:46 What is the purpose of GTKWave?
15:59 iverilog exe compiles the source files
16:06 vvp executable serves as the simulation runtime engine
16:59 How to create a verilog file using VSCode
19:56 module
20:17 half adder sample circuit using gate level modelling design
20:59 inputs
21:09 output ports
21:26 How to instantiate gates
23:23 How to write test bench
25:03 grave accent include compiler directive example
26:06 reg
26:53 How to declare output using wire keyword
29:43 How to code or set the values of inputs
30:03 timescale do not always default to 1 sec
31:26 How to save changes in dumpfile
32:06 vcd means value change dump
32:43 How to record top-level module wire signals using dumpvar
35:16 How to simulate vvp file
35:56 How to view or display the timing diagram using GTKWave
38:29 digital circuits with multiple gates, wires, netlist
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Комментарии
Автор

I watched many videos..Finally this cleared all my doubts and i able to see waves..thank you so much..this is very clear explanation.. plz make more videos

kusumajagini
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You are a good teacher. I watched tones of videos about the same topic but came out more confused. Consider teaching as a carrier because you have a talent. Thank you.

gordononyango
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11:46 my system showing iverilog is not recognised as internal or external command
What to do bro ...plz help me out 😭

ankitthakur
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Very clearly explained and easy to understand the steps .. tq for the video it was helpful for the beginners to learn ..

sushmareddy
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You are a legend in the making boyfriednibluefairy!

botam
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excellent video to get a student started. Thank you for this!

PnDA_pls
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AMAZING VIDEO I WAS SEARCHING FOR A COMPLETE ONE LIKE THIS ITS GREAT HOW YOU HAVE

harihardhik
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@boyfriendnibluefairy Hello. After i use the iverilog -o half_adder_tb.vvp half_adder_tb.v command this pops up
"No top level modules, and no -s option.". I followed all the steps. Why did this happen?

giannismargaris
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your tutorial video is clear enough and very helps, thank you👍

burhanudin
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This introduction is amazing, all the steps are show, well done. Classic shitty tutorial are like "Setup your machine correctly, do 'make' in the console, thank you"

NikHenri
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This was a really awesome video. It helped me to get started with verilog!!!

pranavjain
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Best video about the topic, I thank you so much

marcolanucara
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The terminal "iverilog -v" worked but I still couldn't create file.vvp
Error: Include file half_adder.v not found
I tried removing the line `include "half_adder.v" but it still doesn't work

tuanphan
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Thank you for detailed guide on installing Icarus and GTKWave. I would like to add few points that would help future views

1) If you are facing "not recognised as an internal and external command" go to

2) If clear is not working, use cls

3) make use of if facing "syntax error line 26" just remove last #1

4) if you do not find "terminal" side of ports or console debug, just go to terminal in task bar

Hope it helps

Gateprep
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Thank you Sir, Respect from Bharat (India).🙏

tirth
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half_adder_tb.vvp: Unable to open input file.
facing this problem any soln

rdnd_Year
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i have follow the verilog and vs code installation properly, i cant create a vvp nor vcd file. Please help for this fix thank you!

tayaobilly
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My terminal in VsCode : "Unable to open input file". I tried to follow the instructions but it did not work.

Am I a problem or my terminal? Thank you sir.

trind
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I am not able to create the vvp file. I have added the path in environmental variables. I when i run the command it says invalid module instantiation. Please help

pseudohawk
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@boyfriendnibluefairy video showing proper ways to install and run. i am unable to generate vvp file. i tried the way you have shown . I also tried -v, it shows version which is same as yours. please guide what could be the possible error. ??

dhavalpatel_