Learn Risc-V Assembly Programming - Lesson1 : For absolute beginners!

This is the first in a series of tutorials which will teach you how to get started with RiscV (Risc 5) programming

This tutorial assumes you have no previous experience of programming at all, and teaches assembly using the RARS simulator

All the episodes have a matching text lesson on my website, and you can get the development tools and scripts, and source code as well...

My Books cover most ASM languages and are available on Amazon stores worldwide! Now in Hardback and Large A4 size!
My 1st book covers ASM programming on Z80, 6502, 68000, 8086 and ARM
My 2nd book book covers ARM Thumb, 65816, 6809, PDP-11 and Risc-V CPUs

The Large print versions can be a little hard to find... the links are here:

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My Assembly tutorials cover a wide range of CPU's and Systems, see them all here:

[troyesguerra]

Hello I'm currently taking up an advanced computer architecture class and my professor told me we'll eventually use RISC-V Assembly in a month or two and I'm very glad I saw your video here on Youtube. At least I can start learning RISC-V gradually with your videos so that when the time comes that we'll use it in class, I'll be prepared and have some background knowledge on this assembly language. Thank you so much for the free tutorials!

[BruceHoult]

Quite a good video. I especially liked that you pointed out the difference between things the hardware requires and things that are only conventions. All the registers (except x0) are completely identical as far as the hardware and instruction set is concerned.

ECALL is a real RISC-V instruction. It just calls operating system functions in a similar but more controlled way than JAL. In an emulator such as RARS the ECALL functions might be implemented directly in the emulator. If you're running Linux then the OS kernel handles them. If you're running in an FPGA or embedded board or an emulator such as Spike then you can use a library called "pk" which serializes the arguments and passes them on to the host computer (using the fesvr library) to execute natively. LI and LA are pseudo instructions which expand to ADDI with x0 when possible and LUI;ADDI or AUIPC;ADDI for larger or PC-relative values.

RISC-V assembly language mnemonics are indeed very similar to MIPS but the machine code encodings are totally different. For example immediate values and load/store offsets are only 12 bits vs 16 bits in MIPS. LUI is increased from 16 to 20 bits to compensate. Constants between 4096 and 65535 are fairly rare, and this simple change frees up a lot of opcode space for future ISA extensions.

Amazingly, despite the much simpler instruction set, complete RISC-V programs need a very similar number of instructions and bytes and clock cycles as the same program for ARM or MIPS or x86. When the RISC-V "C" extension is implemented (16 bit versions of the most common instructions) RISC-V programs have only slightly larger size than ARM Thumb2, and 64 bit RISC-V is much smaller than any other 64 bit ISA such as ARM Aarch64 or x86_64. Look for example at the Ubuntu 20.04 release for riscv64, arm64, and amd64 and you'll see RISC-V consistently has the smallest binaries by 20% or so.

The BBC Dr Who board has been out for a few months now, but the same basic E31 CPU is also available in a number of other boards including the HiFive 1 (for more than 4 years already -- I got one in January 2017), LoFive, and two SparkFun RED-V boards, all between about $20 and $60. Chinese boards such as the $4.90 Longan Nano and $10-$25 dual core 64 bit K210 boards such as the MAix BiT and Maixduino have also been available for several years, but can be a bit more poorly documented and generally harder to get started with.

There are quite a lot of Linux-capable RISC-V boards coming this year. The $499 Microchip Icicle is primarily an FPGA development board but has five 64 bit RISC-V cores running at 600 MHz embedded inside the FPGA and comes out of the box with an SD card with Linux. It is available off the shelf now. The $665 HiFive Unmatched is a lot more powerful and comes in Mini-ITX form factor with normal PC features such as a PCIe slot, M.2 etc ready to build a real PC with. The A55-like CPU cores are about half Pi 4 performance (but better then Pi 3), but with 16 GB DDR4 and ability to add a proper modern SSD and Radeon video card of your choice the actual user experience should be around low end Core 2 territory (e.g. original MacBook Air). Currently shipping in June. The most exciting is the Beagle-V, with the same CPU cores as the HiFive Unmatched but only $119 (4 GB) or $149 (8 GB). That's only double Pi prices.

Obviously RISC-V is very new and the boards are nowhere near the same value you get from an ARM board. But prices are decreasing as production volumes increase. Sipeed and Pine64 are promising Pi Zero class RISC-V Linux boards (using the same Allwinner SoC) for $12.50 and "under $10", maybe around the end of the year.

[focuseletronica]

Tava procurando um curso de risc-v quando percebi que tinha um vídeo seu falando sobre. Muito grato por compartilhar conhecimentos. Acredito que você é o cara que tem maior conhecimentos em linguagem de programação de baixo nível aqui do youtube. Grato mesmo!!!

[stevenlalewicz]

Two low cost RISV-V LINUX SBC came onto the market this year Nezha and VisionFive. OK not as cheap as a Raspberry Pi. I've just bought the Nexha to explore RISC-V assembler. Thanks for this series and previous ones too. I've also been programming in ARM and interested in Z80 and it has been great to be able to compare the lots of diffent assembly languages. I have really enjoyed a lot of what you have done. Now to watch the rest of this series.

[kevinclaypool]

This has been super useful for adjusting my asm knowledge away from PIC toward RISC, thanks so much

[chikipichi]

Love the early 2000s look of the website

[chilly]

Hi, great video! Just noticed a small bug in your cheat sheet: jr is not a pseudo for jal, but for jalr

In the : RISC-V Unprivileged ISA V20191213
pseudoinstruction Base Instruction Meaning
jr rs jalr x0, 0(rs) Jump register

[stephenwhite]

Yes, it is very much like MIPS but no delay slot.

[vplp]

thanks, my stupid ass has to do this for university - and even though i know the mentality "RTFM" - i really hate reading that boring thing, so your tutorial is really nice to get to know the basics :D

[krytensp]

Great stuff! I hope you continue this series.

[noname]

ECALL does exist in real hardware. It’s used to issue system calls, so it’s the equivalent of SYSCALL in x86.

[Gigaamped]

I'm very grateful for this video! Way more thorough than my prof ♥

[NasirKhanPAK]

Sir your tutorial on Risc-V is super good. Please make it comprehensive learning material thanks in advance

[charmshri]

Thanks for these videos, very helpful. Wil you please also explain symbols and usage of it in assembly language programming.

[ChibiAkumas]

My Books cover most ASM languages and are available on Amazon stores worldwide! Now in Hardback and Large A4 size!
My 1st book covers ASM programming on Z80, 6502, 68000, 8086 and ARM
My 2nd book book covers ARM Thumb, 65816, 6809, PDP-11 and Risc-V CPUs

The Large print versions can be a little hard to find... the links are here:

[amihart]

Thanks for these, I got the VisionFive to code for.

[giorgosgr]

Can we run RISC-V assembly for learning in a electronic board ;

[andyhu]

Is the 'load immediate 192' command actually translated into two machine commands? I believe that the RISC-V has a 'add immediate to register' command, and by doing so with x0(zero) as one operand register, you CAN load a small number like 192 into a specific register.

[Ata]

What is the name of simulator using for programming?

[theartificial_world]

Hi, I have a small job to do in Risc V assembler but I'm having trouble. Is there someone who is good in this language or even passionate about it to help me?