Pointers in RISC-V Assembly

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In this video, we translate a C program to RISC-V assembly to demonstrate how pointers are declared and referenced. We also use base instructions to set memory locations.

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Timestamps:

00:00 Intro
00:51 RISC-V Simulator
01:33 C Source
02:27 Compiler Optimizations
03:12 Writing ASM by Hand
04:35 32 Bit ISA
05:42 Base Instructions vs Psuedoinstructions
06:30 Load Upper Immediate
08:46 Setting Pointer
10:17 Testing Program
13:38 Dereferencing Pointer
15:40 Store Word Benefits
16:26 Testing Dereference
18:37 Recap

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RISC-V Simulator:

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Only this video preview is the best pointers explanations I have seen before 😂

Nick-xpxd

Your production is incredible, these are so many lain references

AlexanderPrussak

THANK YOU SO MUCH FOR THE VIDEOOOO, i'm so obsessed with risc-v atm 😭😭😭😭😭

bass

clicked on the video and insta-liked because of the preview alone.
thanks for the great content as always, though.

noctiflorous

Hey 👋 can you create a separate playlist for RISC-V assembly as well, I want to start watching all from the beginning and it would be so much helpful and appreciated, thanks 😊

dezashibi

You stated that you are limiting the code to base RISC-V, however the format (syntax) of the instructions you used are in fact pseudoinstructions. This is based on the RISC-V ISA specification. I tried testing your code in the RARS (RISC-V Assembler and Runtime System) and pseudoinstructions must be enabled for the code to assemble.

auralsonicwaves

Adding '#pragma GCC optimize ("O0")' to the beginning of the c-code of the risc-v simulator seems to convince it to not optimize away your example.

atoomnet

Interesting the convention for RISC-V.

mytechnotalent

ok so my stumbling upon this content is really fortuitous because I know very little about programming, but have decided to learn C and MIPS asm for the R3000 the PS1 used so I can learn to decompile Megaman Legends and Serial Experiments Lain for PS1. I don't know if you have any playstation reverse engineering stuff in the pipeline but I would absolutely LOVE that, as this is a bit overwhelming at first!

MistereXMachina

I'm really curious as to why RISC-V Assembly separates the addresses into "upper" high-order bits (most significant part) versus the low-order bits (the least significant part). Is it related to WORD alignment, I wonder?
Also, is this unique to RISC-V or other Assembly languages do it too...?

naelpontes