Types of Assignments In Verilog | Hindi | #verilog #systemverilog #fpga #uvm #cmos #vhdl

In Verilog, an assignment statement is used to set the value of a variable, wire or register. There are three types of assignments in Verilog: blocking assignments, non-blocking assignments, and continuous assignments.

Blocking assignments use the equal sign (=) to assign a value to a variable or register. When a blocking assignment is executed, it completes immediately and the next statement begins executing. The value assigned to the variable or register is immediately available to other parts of the code. A simple example of a blocking assignment in Verilog is
Continuous assignments are used to continuously assign a value to a wire. Continuous assignments are always active and the value of the wire is updated whenever the expression on the right-hand side of the assignment changes. An example of a continuous assignment
Non-blocking assignments use the less-than-equal-to sign to assign a value to a variable or register. Non-blocking assignments are executed at the end of the current time step, so they do not immediately update the value of the variable or register. Instead, the value is scheduled to be updated at the end of the current time step. This allows other operations to continue in the current time step before the value is updated. An example of a non-blocking assignment in Verilog

#digital #learning #digitaldesign #rtl #rtldesign #verilog #verification #verificationengineer #verificationjobs #systemverilog #uvm #semiconductor #semiconductors #semiconductorindustry #semiconductorjobs #semiconductormanufacturing #vlsi #vlsidesign #vlsijobs #vlsitraining #vlsicareer #interviewpreparation #interviewprep #interview #interviewtips #fpga #sta #dft #layout #physicaldesign #circuits #asic #soc