Data types in Verilog | #5 | Introduction | Verilog in English | VLSI

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Data type is a classification that specifies which type of value can be assigned to a variable and what kind of mathematical operation can be applied to the data type.

In Verilog there are mainly two data types
1. Register data type
2. Net data type

Register represents data storage elements. It is a variable that can hold a value. Nets represent connections between hardware elements.
It must be continuously driven i.e. cannot be used to store the values.

Don't miss the HDL introduction chapter:

Introduction to HDL | What is HDL? | #1 | Verilog in English

Level of abstraction in Verilog | #2 | Verilog in English

Modules and Instantiation in Verilog | #3 | Verilog in English

Simulation, Synthesis and Design methodology in Verilog | #4 | Verilog in English

Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar

[manjunatha]

Could you pls make an video on vhdl, entire vhdl topics in one video like how you did for verilog.

[sathyasrirameshkumar]

Please explain port assignments elaborately with example

[amudalagopikrishna]

what is meant by internal net and external net

[Sanjay_Sahu]

Please elaborate some general examples applying for this, my opinion is video length is about 10 minutes is

[ajayvala]

What's different between bit[7:0] and byte??

[_sajalgupta]

Mam can you Please Share the whole Notes Please?

[abdxlive]

Please Explain Internally Reg Externally Wire Or Net & Vice Versa

[sentient]

I didn't understand tri, triand, trior