Washing Machine using Verilog (with code) | Verilog HDL Project by @Dhaval Gupta | FSM | Vivado

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Hello everyone, In this Verilog project, a Washing Machine has been implemented by a friend of mine Mr. Dhaval Gupta in Verilog HDL on Xilinx ISE.
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0:00 Introduction
0:07 Washing Machine with Verilog
1:10 State Diagram
6:07 Verilog Code
10:54 Simulation Output
12:50 Other Projects

#verilog #verilogproject #arjunnarula #electronic

Arjun Narula

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Please find the code in the link description. Any suggestions or queries are most welcomed.
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ArjunNarula

A request, kindly refrain from adding such loud outros. Was listening to his explanation with full sound and then had an intense sound in the ear. Pls do this. It was a great explanation btw.
Thank You

arunpandian

you both did phenomenal work in this collab.😎😎🔥🔥

yuganshibharti

Great project🔥💯
Explanation was amazing👏

adityamehta

Nice presentation God bless you my child

vimminarula

In the "Drain water" condition to repeat itself, the "drain_valve_on" should be 1 rather than 0. Otherwise, the drain will take place just like it is on in the spin condition. Please look at 5:36 timestamp.

sharmaji

Great Project ✨
Informative and well explained Dhaval ✨

ishajain

Nice project and very well explained 💐💫💥

yuktasachdeva

For the first time..
In Drain Water condition, how it can out the drain water if drain_value_on=0 (the dirty water should be present that stage only).

StudioSambasiva

Great project!
Also, the explanation was detailed

SagarKumar-euxu

Great project and very well explained 👏🙌

vaibhavgcool

Awesome explanation and great project. 💯

ritikgupta

Thanks for sharing your useful knowledge!

matinfazel

Amazing work. Really helped a lot! Thanks!

sarthakj

what type of fsm is it mealy or moore?

gurnoorsingh

Great video sir.
Sir, how many basic building blocks did we use in this?

inferno

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