4 Bit Computer Design using Verilog HDL - SAP 1/2 Architecture

Video Presentation of the project, 4-bit Computer Design assigned to me in course EEE 415 (Microprocessor & Embedded System) in Jan 2021 term in the Department of Electrical and Electronic Engineering (EEE) of Bangladesh University of Engineering and Technology (BUET). I was assigned to design a 4-bit computer to perform 16 commands. I was tasked to use Verilog for this purpose. The course instructor was Dr. Sajid Muhaimin Chowdhury.