DVD - Lecture 1d: The Chip Design Flow

Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 1 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).

Lecture 1 covers the motivation for the course and an introduction to the chip design process.
Part 1d gives a quick run through of the chip design flow as a framework for the rest of the course.

Lecture slides can be found on the EnICS Labs web site at:

All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

[qeq]

I can't believe this course is free, Thank you very much Lecture 1 is one of the best introduction to a course i have ever took

[qingyanggu]

Thank you so much for making this course! It is incredibly helpful. I've never had a clearer big-picture understanding of chip design.

[danielpittman]

This course is amazing so far. Even though this is just the introduction, I understand the workflows and separation of labor much more than my prior coursework has led me to believe. I am spending this summer improving my skills and I appreciate this high quality course being provided, thank you!

[alvinloraez]

so far the best free online course for this topic. I am new to IP design and I find this very helpful in my current job. Thank you so much Adi Teman!

[jokofsor]

I wish I had this as I started working on IP design six years ago!
Thanks Adi for making this possible!

[ahmadirtisam]

I don't get the real difference between logic synthesis and design and verification
like we write the code at 2-step for RTL level design then what we do with that design is to convert it into gate level and perform different checks on it like static timing analysis?