Building an FPU In Verilog: Build the Multiplier, Part 1

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Building an FPU using Verilog.

Writing a module to multiply two IEEE 754 16-bit floating point numbers.
Covers multiplying by NaNs, Infinities, and Zeroes.

GitHub repo ...

Special thanks to Dilnaz Kain & Rick Kwan for their feedback during the making of this video.

"Gornin" -- William Rosati
Used by permission

Thumbnail image licensed from Shutterstock.
  1. Chris Larsen
  2. IEEE 754
  3. FPGA
  4. Floating Point
  5. Verilog
  6. Digital Design
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Комментарии
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Another way to make long binary numbers readable in Verilog is adding underscores as delimiters. In 16-bit floats like this:


Verilog ignores these underscores but for human it's much easier!

allmycircuits
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Thanks for the video series, I kinda get confused with so many documents on net.

kunalsolanke
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Sir can you please explain me what is snan, qnan and normal

Gurumurthy