Building an FPU in Verilog: Converting Integers to Float, Testing

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Testing SystemVerilog code to convert 32-bit signed integer to an IEEE 754 binary32 value with rounding.

VIDEO CHAPTERS
00:00 Intro
0:21 Study Question 1 -- Loss of precision from shifting
02:23 Study Question 2a -- Overflow when converting signed integers
03:58 Study Question 2b -- Overflow when converting unsigned integers
08:04 Exercise -- Write code to support the roundTiesToAway rounding attribute
08:34 Test Output
10:34 Test conversion of Zero
10:54 Test conversion of power of 2
11:39 Testing the inexact flag, and adjusting exponent when needed
12:56 Testing roundTiesToEven rounding attribute
14:34 More roundTiesToEven tests
14:58 Wrap-up

Note: Testing numbers with 1 to 31 significant digits really only tests from 2 significant digits up to 31 significant digits. The one significant digit case was tested as part of the powers of 2 test.

"Island Dream" by Chris Haugen
Used by permission
  1. Chris Larsen
  2. IEEE 754
  3. FPGA
  4. Floating Point
  5. Verilog
  6. Digital Design
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