The circuit diagram (see fig.) shows a \'logic combination\' with the states outputs `X,Y` and `Z`

The circuit diagram (see fig.) shows a \'logic combination\' with the states outputs `X,Y` and `Z` given for input `P,Q,R` and `S` all at state `1` (i.e., high). When inputs `P` and `R` change to state `0` i.e., low) with inputs `Q` and `S` still at `1`, the condition of output `X,Y` and `Z` chages to