Whiteboard Wednesdays - A Standard Approach to Lane Margining as Defined by PCIe 4.0

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In this week's Whiteboard Wednesdays video, IP Architect Gopi Krishnamurthy explains the lane margining requirements of the PCI Express 4.0 specification. This spec standardized the previously ad hoc approaches to measuring lane performance in the face of crosstalk, reflection, and jitter caused by process, voltage, and temperature variations.
  1. Cadence Design Systems
  2. PCI Express Controller
  3. PCIe
  4. PCI Express PHY
  5. PCI Express
  6. Cadence
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