Raspberry Pi RP2350 - Testing its FPU and SHA256 Performance

Beyond its general purpose features, the RP2350 includes hardware accelerated SHA256 hashing and the Cortex-M33 includes a full hardware floating point unit (FPU). But how do they perform? Let's find out!
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#garyexplains

[ChromaticReflection]

Gary thank for the quick follow-up on the RP2350 FPU performance. Single precision is the most common use case for DSP applications. In this case according to your data, the RP2350 almost provides 1 FLOP/MHz. This is huge deal and makes DSP applications like audio, digital communications, control, etc very viable on RP2350. The FPU is a huge feature upgrade and for the price, RP2350 is a bargain. It will enable many exciting signal processing projects. Thanks again for running the analysis.

[DQSoft]

The Cortex-M33 cores have the standard ARM single-precision FPU. The RP2350 adds a double-precision coprocessor (DCP), inaccessible from the RISC-C cores.

[Kolyasisan]

Sounds pretty tasty. Wonder how it compares to something like, say, esp32-s3. Purely in raw power, just a curiosity of mine.

[lennartbenschop]

I'm sure that RISCV floating point performance can be improved quite a lot, bringing it close to the performance of the RP2040, which is also a software implementation. Bring hand optimized assembler to RISCV and that should help.According to the RP2350 data sheet the Hazard3 implementation has the M extension (multiply and divide) and it has a fast multiplier.

[relic]

The jump in performance for single point precision calculations is insane! Very excited to get my hands on this processor soon...

[TheOwlman]

Ah Whetstone... KDF9 was one of the first Algol compilers I used over 50 years ago, I feel almost nostalgic!

[the_hetman]

I suspect that the main use for the FPU on the RP2350 is going to be TensorFlow. Cheap devices that can run ML models at the edge are going to become increasingly useful. The extra RAM will help with these workloads too.

[Monk_Duck]

Be interesting to see the impact of the hardware sha2 on throughput of tls or ssh, even though it's just the sha element and not hardware aes or gcm.

[Wren]

Would be interesting to see which floating point software implementation you are measuring. RP2040 has highly optimised soft float in ROM, whereas the RISC-V cores are using whatever junk the compiler provides. You can use the compiler soft float support on RP2040 too (there is a CMake flag) and the performance drops off quite a bit when you do.

[ksbs]

Thanks Gary. Another nice summary video of the new Pico. Frankly I was surprised that the new machine with hardware fpu was not that much faster in double precision (and even in single precision) I was expecting well over two orders of magnitude increase in floating point performance. That's the level of speed increases I remember from 8087 days. Maybe I am misremembering

[Dygear]

I have the challenger board as well. The three pin JST SH connector on the bottom of the board. Is that the SWD port for the RP2350? Any idea if the SHA256 speed will help with HMAC of the top of your head? Just started using HS256 for JWT messages so being able to do that on the Pico would be helpful as I can put the key into the OTP memory and never have to worry about someone extracting it with only booting signed firmware.

[var]

For microprocessors, single precision float is the norm. So in the conclusion I would say the 2350 is not 5x but 7.5x faster than the 2040. (125/16.7=7.5)

[sgodsellify]

Quite a difference in the M33 cores vs the older M0 cores. You said there was no 64 bit hardware in the M33 MCU. Yet double precision is 5x faster using the M33. Interesting. Are you going to be releasing the code that you used for your test?

[suki]

Thank you Gary, for remembering me that we are here on a microcotroller. I seem to confuse it with a "normal" cpu, when i read fpu.

[jacquesmillard]

Great information Gary. I’m guessing these benchmarks are single threaded and only using a single core? If that is the case, the RP2350 with multi threaded floating point operations would be even more significant increase over the RP2040

[slimhazard]

I wonder if a future revision of the RISC-V core will have a way to use the FPU. Apparently using a coprocessor is not precluded, since the SHA256 hardware can be done.

[MisterkeTube]

I'm awaiting someone making a video on why they might have chosen this weird ARM-or- RISCV approach. I would have rather expected the 2 ARM cores and 1 RISCV in parallel. That would have had a benefit, but now I guess most usecases will just stick to 2x ARM, no?

[autohmae]

5:07 ohh, that is interesting indeed !

[doa_form]

Really looking forward for a wireless variant of the RP2350. Sadly it'll probably take a year

[NoToeLong]

Didn't expect the Whetsone benchmark to make an appearance. Real blast from the past.