Writing a Testbench with a Clock in VHDL - #2 Of Testbench Series

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In this video, I will show you how to write a testbench in VHDL for testing an entity with a Clock. The entity we are testing is just an AND gate. And the AND gate output is worked out at the positive edge of the clock cycle.
The coding is done and tested on Xilinx ISE.

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thank you man, i just got a project to do on a basys 3 board and i had no idea how to do such simulation ( teacher has no time to explain everything on a study by correspondence ) and i have only week or two to do a project without a board . Anyways you just saved me with that simulation guide

Rtlehed
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This was a very good example. Could you create a VHDL self checking test-bench.

nitdawg
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Hi, how do you make the clock run for a fixed duration though? I have noticed that the simulation only runs for 1000ns no matter where I try to implement this.

deathmaster