Cadence IC615 Virtuoso Tutorial 14: Using Veriloga in Cadence IC615

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This tutorial demonstrates the procedure for using veriloga in Cadence Virtuoso IC615. The operation of Voltage Dead Band Amplifier (VDBA) is discussed using veriloga.

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Wow... I wish I had known this channel earlier... Thanks a lot, this really helpful...

tatierlina

Dear Sir Nice Lecture with practical exposure using cad tools

sharathbabu

Very helpful! Thank you so much for posting!

arnabsaha

Thank you sir
Please keep posting videos.

ankitha

Will the same code work if I choose Verilog AMS instead of Verilog A at the initial step?

By the way, you are doing a great job. The videos are very helpful. Please keep posting.

RitayanMitraggmu

Sir can you please upload video of implementation of memristor using verilog A code

achyuthprasad

Great video sir, during opening of the application i don't get the option to open with text editor, there is only read VerilogA as an option, how to go about this problem ??

alphabeta

Can we do the same job with Tanner EDA ? If yes, then please share a video for that also.

abhishekacharya

Hello, in my Cadence, the symbol does not create. What should I do?

fatemehshakibaee

Sir..I am getting the error" input.scs 73: the instance I0 is referencing an undefined model or sub circuit, 'KEYWORD_MODEL'. hOW CAN I RESOLVE THIS?

gayathrirajeev

may i dare to request the PDK which you are using in the cad tools? if possible please provide us to do the

sharathbabu

Sir can you please make video on how to use verilog for the same not verilog-A

ashwinjaiswal

Hi, Is that possible to make layout for this? or we need to design an analog amplifier separately? Generally, how can we transfer a HDL (VHDL, Verilog) to a layout?

s.aseif.k

sir I get the error "(TE-4309): extract failed for cellview in cadence how I solve it

pavankori

thank you sir but I get ahdlsim error when i simulate

vijayaveluss

hope you are doing well.
where are you working presently

saidulu

Sir...while creating a new verilog-a file in Cadence virtuoso...its opening as read verilog-a instead of text editor...how to change it to text editor....Thank you

ManojKumar-lihh

how to change the parameters of veriloga directly from the symbol in the schematic view instead of open the veriloga file and modify it?

moustafaali

Any open-source simulator for Verilog-A?

mandarjatkar

Hi sir, can you share me UMC 65nm library pack. so that we can add it to our cadence

MukkuPavanKumarPHD

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