Modules and Instantiation in Verilog | #3 | Verilog in Hindi

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A module is the basic building block in Verilog. A module can be an element or a collection of lower-level design blocks. It provides the required functionality to the higher-level block through its port interface but hides the internal implementation. It provides the flexibility to the designer to modify the module internals without affecting the rest of the design.

Instantiation allows creating a hierarchy in Verilog description. It is a process of creating an object from a module template and the objects are called instances. In Verilog, nesting of module is illegal. One module definition cannot contain another module definition. We can incorporate the copies of another module by instantiating them.

Reference- verilog HDL : A Guide to Digital Design and Synthesis
By Samir palnitkar