How double data rate DRAM works

#RAM #DDR4

[ahreuwu]

this is very well explained, I don't know much about how ram works and how chips work internally but I could still understand almost everything in the video! great video, keep it up

[Cinnabuns]

I'd like to see a logic flow chart for all the timing parameters listed in a motherboard and when they occur, in what order and the dependencies. Command issued, Column access strobe, Row access strobe, Read to Write delay, etc. That would be facsinating especially with QDR/PAM4 on its way.

[neur]

Thanks for bringing up this topic. Never looked at DDR systems.

Regarding phase in Write and Read operations. I am pretty sure you know this, but it wasn't that clear in the video: This is standard for every logic interface I have seen so far.

When writing you need to pull the level to the desired level early enough so it has time to settle (since the change cannot be instantaneous due to capacitance, etc.). This is called setup time (tSU).
Then you need to keep it at this level so that the target can read it (potentially removing some charge). This is called hold time (tH).

When reading, the clock initiates the read. Thus it needs to follow the clock. The time needed is called clock to output time(tCO).

Point is, this is less connected to the memory being dumb and more part of the structure of who sends the clock. So data with sent with the clock normally respects setup and hold. Data requested with the clock, takes tCO.

When combining elements in SDR land, you normally make sure that tCO is longer than tH. That way the output always changes only after the hold time, ensuring no timing violations.

I assume DDR ram uses a multiple of the clock internally and the DDR interface is only there to limit the frequencies on the channel, simplifying connections and routing on the boards).

[andersjjensen]

Nice one Mr. Buildzoid! When you put your mind to it you can actually structure education very well, while keeping it entertaining :)

[wewillrockyou]

"The memory is just kinda there." Basically the story of how DDR won over every other memory system. It's also becoming one of the biggest downsides to this type of memory system and why the likes of HBM and IBMs Centaur buffered memory exist.

[MSquared]

Your videos are wine that ages gracefully with time. Example when doing RX Vega water cooling / tuning, your videos held much greater revelancy and insight once you get deep in the topic presented that may be missed by some upon initial viewing. Keep up the great content.

[Dave]

Just a quick note: DQ is D (an input) during a write operation, or Q (an output) during a read operation. Saying data queue is not technically accurate, although the data is either going into a pipeline (writes) or coming from a pipeline (reads). The pipeline is why the differential clock CK_c/CK_t is required. The DQS_c.DQS_c is responsible for transferring the input data D to the pipeline, or transferring the output data Q to the output buffers.

Edit: The 90 degree phase shift for the read clock is there because it is necessary to allow the data enough time to travel from the output buffers of the RAM chips to the inputs of the memory controller.

[mroutcast]

Would love to see overclocking guide - basically going over all the timings and sub-timings - talking briefly what they do, how important they are for performance and how to determine stable operational values and how voltage plays into all this. Because say I'm going for 3600Mbps - how do I know where to aim with either sub-timing for this memory speed, etc.

[asm_nop]

I love how DDR memory internally behaves how you would expect QDR memory to behave from a high-level description.

[Elessar_Telcontar]

I have greatly enjoyed all the deep dives into ram

[goldnoob]

In fact, it's mandatory to setup data some ps ahead so the target chip is sure to get valid data un it's input buffer for sampling. This is always specified on the data sheet.
On RS232 the appropriate time to sample is right in the middle of the clock.
The functionning is well explained great video !

[hatsuneadc]

Finally the video I've been wanting for quite some time

[robertboyer]

I'd love to see this in relation to drive strengths, on-die termination and setup times. What happens to the signals when things are not configured properly in bios.

[GodmanchesterGoblin]

Informative. I did not know about the shifted sampling clock for the read data timings. However, to me as a digital designer from the 1980s and as a multi-layer PCB designer from the 1990s, the really hard bit to get my head around is how they maintain data integrity with up to 64 single-ended data lines on a module all switching at up to 3600 mega-transitions per second or more. Differential is easy (relatively), but single-ended, bi-directional signals...? sheeesh...

[kennethnoga]

thank you for this just got an aqua z690 oc, and i never overclocked memory before. This was very timely should be fully built in a few days.

[joseperez-igyu]

Very interesting video BZ! Somewhat different than other videos you have put out. Keep us on our toes BZ! Appreciate it!😃

[Lets_get_wealthy]

Loved this video. Gonna watch the rest of the series tomorrow

[andyhelipilot]

Quality video. Thank you. Amazing very useful and extremely interesting. Thank you

[jamesjamey]

Hey! Thank you for all the good information!

[rawdez_]

13:20 OH NO!!! THE FANCY ONES!!! everybody, find cover!
thanks, thats a very informative video, bz, cheers, have a great day!