How to Control 7-Segment Displays on Basys3 FPGA using Verilog in Vivado

Using the Digilent Basys3 reference manual and a demonstration circuit implemented on the FPGA, just wanted to explain the logic behind driving the 7-segment displays on the Basys3, such as I have done in previous videos.

UPDATE: The calculation for the 1ms refresh period is not accurate. For the refresh period the calculation should consider the following:
A 100MHz clock has a period of 10ns, that is 10 x 10^-9 seconds or 1 second / 100,000,000. Therefore, to achieve a period of 1ms, 10ns is multiplied by 100,000. So, 100,000 ticks of the 100MHz clock is equal to 1ms. So, for example, to achieve a refresh period of 2ms the calculation for the digit_timer should be 10ns x 200,000 = 2ms. So, 200,000 ticks of the 100MHz clock is a period of 2ms. So, for a 2ms digit refresh period, the digit_timer would count to 199,999 and then reset and switch to the next digit_select. Sorry for the confusion.

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[alexbeckes]

great video. I was stuck on how to control the seven segments individually and this was the only video i found that explained it

[Avionics]

Great video thanks. I found the hard way about 7 segment display on basys3 when i first started playing a month ago. so i ended up reversing the pattern by putting the 'a' on the right hand side and 'g' on the left. I am new to verilog and FPGA :-).

[timmorgan]

Great stuff - Most informative - Thanks for putting it out - Cheers :)

[AryanSingh-vzuu]

Hello, can you explain how can we simulate (seven segment led display) using testbench. For this very code.

[nivenesan]

Variable 'digit' should not be used in output port connection

what does this error mean? Im getting this error in top module?

[maazmahmood]

Wonderful Video, Can you pls explain that what is the use of Refreshing Rate or Refreshing Period?

[abhishekss]

Hey great video, but i am stuck at one issue, i think maybe you can help me?

[SShiJie]

Im trying to figure out how to turn on one DP for one digit in the 7 segment display, so far im having no luck still

[cagatayyigit]

14 bits binary to its 4 digits:


module bin2dec_digits(
input clk_10Hz,
input [13:0] in,
output reg [3:0] ones, tens, hundreds, thousands
);

always @(posedge clk_10Hz) begin
ones <= in% 10;
tens <= (in/ 10) % 10;
hundreds <= (in/ 100) % 10;
thousands <= (in/ 1000) % 10;
end

endmodule

[cthutu]

You do not need to reverse endianness or reverse the indices in the xdc. They will still connect to the correct outputs.

[deathmaster]

Hi, I seem to be getting a NSTD-1 and UCIO-1 errors when following this method step by step while trying to generate the bit-stream at the end. Any idea why that could happen? I checked the forums and I did find entries on those errors but I could not make head or tails of what they actually meant

[sankasuvarna]

Hi bro u r videos are actually superb i am doing project real time clk(hr:min:sec) using 7 segment display and also i need to convert 24 hrs format into 12 hrs pls help to do this

[danielafajardo]

Hello. I didn't understand why we need a 10 Hz clock. Could someone explain that to me, please?

[navaneethkrishnannampoothi]

Bro can you say how to show a constant number on the LED. For Example I have to keep showing the number 999

[dantecraft]

Use this testbench to check it in simulation
`timescale 1ns / 1ps

module testbench;

reg clk_100MHz, reset;
reg up;
reg down;
wire[6:0] seg;
wire[2:0] digit;

top counter(clk_100MHz, reset, up, down, seg, digit);

always begin
clk_100MHz = 1'b1;
#10; clk_100MHz = 1'b0;
#10;
end

initial begin
up = "0"; down = "0";reset = "1";
#15; reset = "0";

#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";
#20; up = "1"; down = "0";
#20; up = "0"; down = "0";


#20; up = "0"; down = "0";reset = "1";
#15; reset = "0";


#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
#20; up = "0"; down = "0";
#20; up = "0"; down = "1";
end
endmodule


but sec and digit stay at a fixed value without changing, is my testbench wrong?