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Espresso and Electronics - 10X Better Bug Detection with SimAI
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Spectre Language Command
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What Is Logic Equivalence Checking in VLSI Design
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Espresso and Electronics – Quick Sips of EDA Wisdom
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Cadence Subsystem IP for PCIe 6.0 and CXL 3.0
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Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics
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Cadence Demonstration of Time-of-Flight Decoding on the Tensilica Vision Q7 DSP
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Mastering the Basics Essential Editing Tips for an OrCAD X Capture Project
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How to run the online and Batch Design Rule Checks DRCs in OrCAD X Capture Schematic
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What is Hierarchical Design and How to Synchronize a Hierarchical Block in OrCAD X Capture Schematic
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Different Techniques for Connecting Wires in the OrCAD X Capture Schematic
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How to Modify DesignTrue DFM Templates and Add DFM Values to the Constraint Manager
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How to Identify Missing Soldermask and Pastemask in Padstacks using Allegro X DesignTrue DFM
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The more you know, the faster you go. Accelerated Learning
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Cadence Raises the LGBTQIA+ Pride Flag!
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What is Digital Verification
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Hierarchy in EM Extraction in Cadence AWR Microwave Office
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How to Setup Symbol Representation and Control the Visibility of Symbols in 3D Canvas
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How to Crossprobe and Highlight Between PCB Editor and 3D Canvas
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embedded world 2024: Using Low-Power DSPs for In-Cabin Sensing
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Quantus I-DSPF Output Demo Series: Episode 3 (In-Context Probing)
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Viewing Spectre Documentation in Doc Assistant
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What Is MBIST
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At speed testing with OPCG Solution
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