Introduction to FPGA Part 4 - Clocks and Procedural Assignments | Digi-Key Electronics

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.

In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).

We start by showing how the D flip-flop in an FPGA logic cell can be used to store a 1-bit value for one or (potentially) more clock cycles. Multiple D flip-flops can be combined with combinational logic gates to create hardware circuits that operate sequentially. We can control this sequential logic through Verilog blocks known as “procedural assignment statements.”

Next, we demonstrate a procedural assignment statement by constructing a simple 4-bit counter inside of an “always block.” Each time a button is pressed, the value increments by 1. The counter value is shown on the LEDs (in binary).

Note that you will likely experience button bounce that we have not accounted for in the demonstration. As a result, the counter will likely skip values each button press. You would need to implement button debounce circuitry (either in hardware or in HDL) to correct for this behavior. We will cover button debounce in a future episode.

Your challenge is to create a clock divider for the onboard 12 MHz oscillator (assuming you are using the iCEstick, the 12 MHz oscillator is connected to pin 21). The clock should be divided to 1 Hz, and this new clock signal should run the counter shown in the video. The new counter should increment on its own once per second.

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[aquaehelveticae]

Hi Shawn, your videos (particularly those in this FPGA series) are awesome! You are one of the very few tech video authors who manage to hit the sweet spot of exactly the right amount of detail which is both thorough enough for newbies to follow and moving along fast enough to keep even the more experienced audience attentive. One can tell that you have a huge didactic talent by how you structure and present your lessons and pick well-thought-out examples. But _please_ don't talk about "debouncing" when you actually mean the "bouncing" of a mechanical switch – de-bouncing is the process of _removing_ the bouncing!

[davidkempton]

Just had to tell you that I got the 1Hz counter working. It took a bit of working out but was extremely satisfying when it worked. Thanks Shawn!!

[iwbnwif]

Perfect timing (no pun intended) - finished Parts 1 - 3 yesterday and hoping the next part would come out soon.

[vasileceteras]

This series is the reason I've subscribed to the channel, great material and presentation!

[electronichome]

I did the assignment, but I needed the Google's help to keep the syntax correct and to read more about wires, registers and other types and declarations, because my first codes simply did not compile. Then I realise, that I can start from a "working code" that compiles without error and type my code in steps, where after each step I am trying to compile the code and verify if it's correct. Thus actually I've learned a lot about Verilog. And I like it's C-like structure.
However, for the internal clock divider down to 1Hz I needed to "steal" some ideas in the web, because I've had troubles to put this procedure inside the code without build-error and my approach with two modules was wrong, also the declaration of variables and registers was not initially correct. But I'm happy I did it, after 1 hour fight with Verilog. Now I am going to check Shawn's solution and go for lecture 5!
Thanks Shawn!

[Tarbard]

Your videos are wonderful and you are a great asset to digikey

[AhmadAsmndr]

I really appreciate your effort, it is amazing the way how you teach. I did make a search to learn how to use and divide CLK Signal in FPGA and I did the blink program first and lay it out as my template for the next projects, and then I did solve the challenge . Thank you very much.

[roshandsouza]

Very interesting, can't wait for next video! Big thanks!!

[leninorihuela]

Thanks for lot of information, summary and sort tahnk you so much

[internetvideoenjoyer]

Thank you for this, it was great to see the counter working, it's a really nice demonstration.

[Tristoo]

once again, excellent video, thank you

[skaterfabi]

Pls show an uart implementation in a future video. Thx for the great content.

[vaniaeli]

Muito Obrigado por democratizar esse conhecimento ❤

[NishantjonyJaiswal]

Q1 =Q0/2, and
Q2=Q1/2 or Q0/4 and so on.
so is counter also frequency divider?

[CrimsonTide]

What would happen if, instead of a single always block, we had two always blocks, one for rst and the second for clk? Was there a particular reason they were combined into a single always block apart from convenience?

[TinLethax]

Finally a good video to get started with FPGA! I'm waiting for the ice40 BRAM topic too.

[conorstewart]

Just wanted to point out that in an always block it doesnt necessarily execute sequentially. It will execute everything in the always block on the clock signal so if you had multiple assignments in one always block they will execute in parallel. Might also be worth mentioning blocking and nonblocking assignments, because <= doesnt just mean it gets that value, because you can also use = but they do different things.

[bertbrecht]

Do you know who else has these FPGA boards in stock? I am eager to get started on this series.

[byronwatkins]

Can a Verilog module have multiple always blocks? If so, why not have different blocks for the reset and clock?

[davidkempton]

When are you planning to release the next episode in this series on FPGA's?