3D Stacked Transistors: Improving Area By Building Upward | Intel Technology

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3D Stacked Transistors: Improving area by building upward | Intel Technology

[Alex-oqyg]

This is big, huge performance jump + increased efficiency

[StRM]

finally intel making process with a CEO engineer

[EnochGitongaKimathi]

I think the reason intel delayed at 10nm was they tried to implement too many technologies simultaneously; Superfin, RibbonFET, PowerVia. Glad to see they now have a better update rollout. With High-Na EUV round the corner, the combined manufacturing future tech is very impressive. Makes you wonder what sort of experiences devices and technology will offer in just half a decade.

[azamatbezhan]

How do you think what technolgy node will get first high k/ metal gate instead SiO2

[JorgetePanete]

Is it better to stack horizontal transistors or to use vertical ones?

[Speak_Out_and_Remove_All_Doubt]

Feel free to send me any future processors and I'll test them for you 😉

[HouseOfFunQM]

Anyone here today, where this just DIDN’T HAPPEN and every semiconductor company basically abandoned the technology?

[carl]

Sounds similar to IBM's VFETs. Stacking logic on top of each other, instead of increasing die area. Fascinating stuff.

[henrywojcik]

I wonder if silicon wafers are needed then any more? It seems all Si is epitaxially grown then.

[whoisthis]

physicals fusions but usually physics=big mcunopes

[Youcanatme]

Isn’t intel far behind tsmc? TSMC seems to always have better quality

[bbloem]

Intel beating samsung and tsmc to the punch💪💪