Demystifying 5G – Clock input monitoring, holdover and relocking in 5G base stations

Clock input monitoring and a corresponding holdover mechanism in case of a loss of the external clock signal are key functions in 5G base stations. The video demonstrates an IDT clock generator and shows the measurement of phase transient during a locked-holdover-relocking-locked cycle. A clock signal with a defined phase noise profile is used to emulate the effect of a real-world clock with a non-ideal phase noise performance.
The demystifying 5G video series discusses main topics related to 5G including requirements, timeline, frequency bands and key components.

IDT 8V97003 RF Synthesizer:

IDT 8V19N880 RF sampling clock generator: