Introduction to Direct Memory Access (DMA)

#DMA #Xilinx #XAXIDMA
In this Video we will have a general over view of direct memory access (DMA). I will also introduce the Xilinx X_AXI_DMA IP core, which we will use in the subsequent tutorials. DMA is an important concept in developing high-speed hardware accelerators.

[dipeshpatil]

I have seen many videos explaining DMA, and this is by far the best explanation. Continue doing the good work sir.

[mehdimadadizadeh]

It is one of the best videos about the DMA controller I have ever seen. Thanks

[learnmath]

Very nicely explained..!!! Thanks Vipin.

[takieddine]

Hi Sir, thanks for this tutorial, do you have a video about DMA SG mode ?

[sugee]

Thank you for the tutorial. Question: When doing the DMA transfer as you show with the Zynq through either the GP or HP slave interfaces, how is the DMA access to DDR assured to be coherent with the CPUs?

[tomo]

In the C2H channel as per page 22 of UG 195, it’s the application that initiates the transfer. Assuming that it’s the card(FPGA) that wants to pass data, how does it happen via C2H DMA channels (The application does not know when exactly the card wants to send data?

[abhirampadikkat]

Sir, i have heard that exception handling is difficult in dma data transfer, can you please explain that... Thankyou sir, this vedio gave me a clear understanting on the concept... hope you will reply🌝🙌🏻

[vijaydattu]

Hello vipin, Thank you for explanation
How to trigger 2 separate axi dma's which are connected to 2 separate ddr's chips?

[jigar]

Thanks for the amazing Lecture. I have one doubt though! For non-memory mapped devices, while configuring the DMAC why don't we give a destination address. I know IO devices are on a separate bus than CPU, DMAC. So the address wont be a address from system bus address space. But IO Devices might have lots of lots of registers, and if we just want to program a few, how do we say that to DMAC without passing destination address. Since we have direction set and DMAC understands the interconnect between itself and IODEVICE, it should be able to use that destination address in the IODevice address space. Thank in advance for your answer!

[arv_sajeev]

Wonderful explanation, I had a doubt though, is the DMA controller a centralized one for all peripherals of the system or are there multiple DMA controllers? how is it usual done in a modern day system?

[patthimahendhar]

What a bout iommu in which configuration it is present

[pavankalyantechincal]

Hai sir any idea on DMA register re Intilization

[vijaykumarmakala]

Hi Vipin,

Very well explained. I have doubt. You said that when DMA is taking care of the data transfer between the memory and the peripheral/device, the CPU can do other tasks in parallel. But the BUS(address/data/control) can only be used by a single device. Than how can CPU work on a different task in parallel.

[patthimahendhar]

Very good info I got a clarity in the same way can you brief pci connection to the processor

[eitangidanian]

Hey Vipin, can you please send Presentation of DMA ?

[abhijitkumar]

Sir, how can a single system bus support all AXI protocol(Lite, Stream, Full) at the same time during DMA? or are there individual buses for each?

[kavinduvindikasomadasa]

Why is there only one system bus?...in zynq ultrascale+ architecture we can directly connect PS with peripherals using M_AXI_GPx ports...when it comes to DMA connection to DRAM controller, we are using S_AXI_HPx ports....therefore we can use 2 system buses where PS and DMA can do the communication with peripherals at the same time. Am I right in this point?...

[Andrew-egpc]

The DMA module is part of the PS(ZYNQ) (not PL FPGA), right? Is there any code example of doing burst read/write using DMA?

[patthimahendhar]

Please tell me what about cache sync after dma operation

[sandeepm]

Can i have a pdf version on the above video