From top to Transistors: opensource Verilog to ASIC flow

Go from HDL to physical CMOS layout right now with open-source tools, by following this HOWTO guide and demo. When things go well, the design can be converted to GDS for ASIC fabrication in a single step. I also show how we can dig deeper, using yosys, openlane and openroad, when the hardening processes isn't quite as simple.

This is part of my journey through the zero to ASIC course, so I don't have all the answers, but have found some interesting bits already. Let me know if you see mistakes, or have hints! I'll be updating the ASIC playlist with more as I progress.

** Links of interest **
Details, written instructions, downloads:

My fork of the demo structure, with the Makefile used in the video:

OpenLane:

TinyTapeout:

[gabrielbarrientos]

Man! Great videos!!! The way you explain the workflow and the different levels of abstraction is just so cool!

[friskydingo]

Recently subscribed. Defantaly informative. Super cool stuff. 👍

[runforitman]

Very much appreciate this
Im trying to go from FPGA to ASIC and found the software overwhelming
But your videos are really helpful in giving me a sense of direction

[amop]

Great video! Both entertaining AND informative!?

[CalvBore]

Hey, awesome video! was really neat to see you work through some of the errors that openlane was giving you. I just found openlane a few days ago. Would be really cool to see you g through the flow with openlane2! Have you managed to make any designs that incorporated analog components? I think it'd be super interesting to get a PUF into a design. Would love to see more openlane videos from you!

[JohnathanSammer]

thats quite amazing - how many bits was the frequency counter and how fast could it clock itself.

[atosheislam]

Hello Sir, are there i/o pads are included in the design? How to add pads in the design? One more thing, after getting the gds file, how to see the hierarchal view of chip (like pads, different modules, top view)... Thank you

[maylermartins]

Hi, nice video! About the congestion, you can get the instance name in the congested area and do a grep in the mapped verilog. That you give +- an idea what module (and surroundings) are congested. Usually cells from the same module are placed together. However, I am not sure what is the strategy for the name composition in the physical synthesis. I would guess module_name_inst_name.

[modernsolutions]

Gosh you look amazing.
What routines of yours/things you do would you say are most responsible for your good looks?
sorry for the odd question. I didn't have a had a dad who taught me how to look like i care about myself.

[MohamadAbdallah-lm]

Hello, I'm really interested in this topic overall but I don't know where to get started (I'm trying to figure out whether this is a career I want to pursue)
Any help would be greatly appreciated
Some background on me :
I'm currently a third year computer engineering student and I'm trying to find if software or hardware fits me more
Thanks again!

[tombouie]

Thks buts ?why do all the super-smart open-source folks have super long hair?.
if I grow super long hair, I justs-mights gets-smarts too ;)