Comparing ARM vs RISC-V vs x86_64 with GCC vs Clang

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How do GCC and Clang compare when generating ARM, RISC-V and x86_64 code?

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[ycombinator]

This was so fun to watch even tho I only understood 30% or so of it. This tells me how much I have yet to learn. Thanks for posting this

[vytah]

20:20 on some CPUs POPCNT has false dependency on the destination register, so the XOR lets the CPU to schedule POPCNT earlier. GCC added this workaround in 2014, see the issue 62011 on GCC Bugzilla. The comments there suggest that this might be fixed on newer CPUs, but I haven't found a direct confirmation yet.

[johanmyreen]

05:09 The RISC-V architecture defines 32 registers named x0 to x31. x0 is always read as 0, and writes to x0 are discarded. The a0 register is actually an alias for x10. Every register has an alias name, and the aliases reflect the usage of the registers in the standard calling convention ABI. For example, the return address register is x1 and has an ABI name ra, x2 is used as the stack pointer and has the ABI name sp, and so on. The "a" registers a0-a7 (x10-x17) are used for function arguments and return values (a0-a1).

[theIpatix]

24:35 I think this is because clang believes the target risc-v doesn't have the hardware floating point extensions. I'm fairly certain that for other architectures gcc nor clang usually inline software emulation of missing hardware features. Probably because this allows embedded developers to use custom implementations for things like divisions or floating point.

[Arthur-qvnp]

@21:35 RISC-V actually has a popcount instruction, it's located in extension B (Bitmanip).
In order to use it you must add "b_zbb" to the "march" option.

[Quarky_]

I think it's RISC 5 since it's the fifth version of the original RISC ISA.

[perpetualrabbit]

So, two years later, how has the situation changed with RISC-V Vector 1.0 extension support in GCC anc CLANG?

[bobweiram]

Was it "Computer Architecture: a quantitative approach." John Hennessy and David Patterson?

[theexplosionist]

popcnt had a false dependancy on skylake, fixed in sunny cove.and onwards hence xor eax, eax

[Malephex]

Was it "Universal Assembly Language", Fitz and Crocket 1986?

[Omnifarious]

18:52 - I'm guessing that gcc's Risc-V code will be faster. There is a micro-parallelization opportunity here involving doing the add and shift at the same time in different ALU units. If you do things the way clang is doing them, you're forcing a false serialization because of the way a register is being re-used.

I suspect (from my limited understanding of exactly how the hardware works) that a really good instruction pipeline handler would notice this and re-arrange things to remove the false data dependence. But, a less sophisticated one wouldn't.

[dascandy]

@5:30 you're returning a 64-bit integer, but the instruction for loading a 32-bit value into the 32-bit half also zeroes the top half, making it smaller to encode.

[AndrewRoberts]

For future videos, can you please turn off DARK MODE, as makes viewing in a mobile screen almost impossible.

[volodymyrdobrovolsky]

Dear Mark. Sans this "magnificent eight" the RISC-V will show very low performance, and will not reach the technical level of Intel/AMD/ARM. My MHP RISC architecture is far ahead, for it do not need "magnificent eight" at all.

[waynes]

Still don't understand why ARM is efficient. It still has more instructions on average to handle right ?

[volodymyrdobrovolsky]

The RISC-V is based on 40-year old ideas as RISC-V Foundation claims. There is no sense to port the huge x86 and ARM software ecosystems on it. Thus, RISC-V will never gain a victory over x86 and ARM. The most of positives about the RISC-V processor are arbitrary speculations. The advantage of RISC-V is open architecture. RISC-V has instructions of variable lengths. This is bad, it is a departure from the RISC architecture principles.
The Contemporary microprocessors contain 8 specific hardware components: (1) SMT (Simultaneous Multithreading), (2) register renaming, (3) instruction reordering, (4) out-of-order execution, (5) speculative execution, (6) superscalar execution, (7) delayed branch, (8) branch prediction. These components make up some kind of a “magnificent eight” of components which essentially raise the performance of microprocessors. But unfortunately they are very complex. A processor core having these components is a full-fledged one, otherwise it is good for simple applications, e. g. for embedded systems.
The “magnificent eight” of components is very hard to design, only the experienced firms and developers are able to do this, and much know-how was acquired, some effective solutions are patented. Particularly complex is the SMT. Only powerful and advanced firms like Intel, AMD, IBM are able to equip their processors with the “magnificent eight” components. It is not surprising that some Intel processors, and the famous Apple's M1 processor do not contain SMTs. If a company is able create the full-fledged RISC-V processor with all “magnificent eight” components then it would be a serious achievement, and such RISC-V would be considered of the World's class comparable with x86, with ARM, but not more. As far as I understand most of the developed RISC-V processors have no components from the “magnificent eight”, and are intended for embedded systems.
A course directed on further development of RISC-V is a wrong way, and leads the computer architecture to deadlock. The RISC-V is not perspective for computer industry. The World demands absolutely novel microprocessor having much more higher performance than all contemporary ones. The novel and effective ideas on computer architectures do exist! Here’s such a novel processor architecture:
V. K. Dobrovolskyi. Microprocessor Based on the Minimal Hardware Principle. Electronic Modeling, 2019, vol 41, No 6. pp. 77-90. The article is posted (under the Cyrillic name добровольский.pdf):
This processor does not have the “magnificent eight”, it is not necessary at all. This comment reflects different view on the RISC-V architecture, and the computer community has a right to become familiar with such a view. I’m Volodymyr Dobrovolskyi.