FPGA Clock and timing concepts explained simply for beginners using two analogies!

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Hi, I'm Stacey and in this video I'll explain clock and timing concepts using two simple analogies:
The factory, and the stop motion movie!

Google form to give me your feedback:
Ending music: Faith by David van Niekerk

0:00 Intro
0:38 The factory: Intro
2:13 The factory: Timing analysis and closure
4:10 The factory: Strategies for meeting timing
5:02 The stop motion movie: Intro
5:52 The stop motion movie: Setup and hold times
7:08 Balancing combinitiorial logic and pipeline registers

  1. FPGAs for Beginners
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FPGA Clock and timing concepts explained simply for beginners using two analogies!

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Комментарии
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I generally percieve these things like my laundary, -- placing clothes, starting machine, drying the clothes and ironing. Fits well with the pipelining concepts too.

satpatel
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I'm glad you produced this video. I have an Counter AXIS IP to a FIFO to AXI DMA to ZYNQ PS on a Zedboard and couldn't meet timing until I slowed the F_CLK0 down to 80 MHz from 100MHz. I'm not sure which worker is having trouble putting on the lids though :)

Leethal
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Came from reddit, seems like I will be here for a long time :D

arinoba
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Great analogies! Enjoying your short and easy-to-understand videos!

satpatel
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Hi, I’ve been following your videos, and they are really good. I wanted to ask for a favor, if you don’t mind. Could you please make another video on STA with a real-time example, such as a FIFO or some protocols? In that video, it would be great if you could explain how to solve timing issues like negative slack, setup, and hold time violations.

boyillahareeshreddy
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One analogy is that using synchronous clocking as far as possible and abstaining global reset In sequential circuits.

jogeshsingh
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Before the next snapshot clock, where we are busy doing stuff to get ready (and make sure that our hands are not in the way), is there another clock used here aside from the main snapshot clock?

eigenfield