[Synthesis/STA] fixing setup and hold timing concepts

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fixing Setup and hold violation
fix setup and hold violation

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Awesome explanation....the most liked part in the lecture is explaining in practical way..

durgaprasadnaredla

Sir, At 11:18
For hold, we should check at launch flop itself, as you discussed in previous videos
So buffer should add before launch FF not after launch FF?

Plaese clarify this doubt, sir

mahaboobpeershaik

if there is no combinational circuit in between. but still we have set up time violation how to fix it by tel designer

poojaugare

its means Hold is decided at the time of design, not after that but we can fix the setup after design completed ???

omprakashchoudhary

How are the rise and fall time are affected by adding the buffer?

ankitasharma

Gajab sir maja agya aur video daliye na

ShubhamPandey-bgvx

can we add the buffer exact before the clock pin of capture flop that buffer will not affect the next one

aniketsangamwar

Sir, is setup and hold violations can occur in the same path ?

saijagadeesh

[Synthesis/STA] fixing setup and hold timing concepts

[Synthesis/STA] fixing setup and hold timing concepts

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