FPGA BCD to 7 Segment Decoder (7 segment display) Lab 2

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This simple computational logic project performs as a BCD to 7 segment decoder. It is a mixed schematic and VHDL design -- the decoder logic block is implemented in VHDL. Displayed so that a difference in & Segment Display is visually apparent.

Compe 490 Lab 2
  1. John Ervin
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