News Corner | AMD Zen 2 Exposed, AGESA Clock Speed Boosts? Skylake-X Price Cuts?

News Topics:
00:00 - A Look Inside AMD’s 64-Core Epyc CPU
04:43 - New Ryzen AGESA Allegedly Boosts Clock Speeds
06:51 - Gigabyte Teases TRX40 Motherboard
07:45 - TSMC 5nm on Track for 2020
09:12 - Intel to Cut Skylake-X Pricing?
10:26 - Razer and Xiaomi Enter Gaming Monitor Market
12:26 - Team Group Launches 32GB DIMMs

Sources:

News Corner 77 | AMD Zen 2 Exposed, AGESA Clock Speed Boosts? Skylake-X Price Cuts?

Disclaimer: Any pricing information shown or mentioned in this video was accurate at the time of video production, and may have since changed

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[Krazie-Ivan]

Tim, have you noticed "Freesync" branding has been disappearing from monitor titles/specs/advert materials, replaced with "G-sync Compatible"? Nvidia's term for allowing their cards to function with Adaptive-sync seems rather misleading alone, but combined with removal of "Freesync" ...wtf is going on?!

[michaelr]

I like my morning coffee with Hardware unboxed, but that's just me

[dava]

I was expecting some kind of Zen 2 scandal! you let me down Hardware Unboxed!

[Xandergre]

10 pm in Greece, what a perfect time for a news corner keep it up guys!!

[CaveyMoth]

"Nobody's using DDR4 2666. . ."
Jayztwocents: "Am I a joke to you?"

[pweddy]

It's fascinating the Zen cores use as much if not more space for cache as they do for the CPU cores!

[djsnowpdx]

I live in the U.S and I prefer when the videos are waiting for me at 4 AM when I get up. You’re almost the only channel which does that.

[johnm]

3:09 Rome has 129 PCIe lanes. The extra one is for a System Management Controller.

[glenwaldrop]

8.4 billion transistors in an IO die?

Wow.

Tech has come a long way.

The 486 was the first chip to break 1 million transistors in 1989.

Today we have 8.4 billion in the chip that juggles data for the chips that do the work.

[Noobsaucer]

Whatever time works for you guys and the algorithm and whatnot! You post, I watch. It's that simple.

[scottstamm]

The Ryzen IO quarter size die doesn't look like a cut down version of the Epyc IO die. If you compare the two, there are quite a few differences. I'm not saying it's not a cut down version of it, it definitely is, but it's not a Epyc IO die cut in quarters, it's its own IO die design all together.

[BAdventures]

Enjoyed the breakdown of the IR photos at the start. Good updates as usual.

[goka]

This is a way better time to upload, thank you!

[Cooe.]

The center is a big block of SRAM, likely used for some kind of memory address caching to help cover the latency of having the memory controller on a different die vs the CPU cores themselves.

[janpul]

It's 9:20pm in the Netherlands, excellent timing!

[johnm]

4:02 Ryzen does have 32 PCIe lanes. The limiting factor is the AM4 socket. It always has been.

[Xaltar_]

Loved the die pics, interesting stuff for sure. I would guess the large central area is a combination of cache and further infinity fabric backend to handle the CPU chiplet interconnects. I am by no means an expert though.

[SuprizePlayz]

10PM Germany, where you at German Squad? :D

[ryansample]

8PM over here in the UK when I saw this. Pretty nice time.

[TheEVEInspiration]

That middle block is the NSA section :)