The Critical FPGA Basics: Always blocks, Inferred latches, and why the FPGA needs a clock, anyway?!

Hi, I'm Stacey, and in this video I talk about everything from asynchronous logic, why the FPGA even needs a clock, and inferred latches!

0:00 Intro
0:38 Always blocks
8:27: Why the FPGA needs a clock, and static timing analysis
13:00 Registers and their function
16:00 Synchronus and Asynchronus logic
18:40 Asynchronus loopback paths and inferred latches
23:50 Avoiding inferred latches
27:05 Summary
28:56 Outro

[bigGuyubuntu]

Lovely video! you're the best when it comes to FPGAs!
Can you make a video about Dynamic Function Exchange (Partial Reconfiguration) please?

[e]

I didn't know about this new series ! As an embedded engineer (not fpga, more MCU, MPU) they get me a feel for the field! Thanks Stacey

[heliumlabs]

Thanks Stacy! That is an extremely valuable, amazing, simplified yet explanatory video. Thanks so much for your time making these videos. Please keep them coming. I know these vids are'nt the best return of your valuable time so if you need assistance to offload some work, please let us know and we can contribute what we can to keep them coming. Have a blessed day

[aakarshithasuresh]

Loved this video stacey! Your way of looking at systemverilog and why we use certain constructs in certain way, is amazing, easy to understand and remember too. Thanks a ton....😇

[wolpumba]

*Summary*

This video explains FPGA programming fundamentals, particularly for those with a software background, emphasizing that FPGAs describe circuits, not traditional programs.

*Here are the key takeaways:*

* *0:00** - Intro*
* *0:38** - Always blocks:*
* Have two main functions: defining signal behavior (logic) and registering the signal (clocking).
* The clock in a synchronous always block helps create predictable timing and avoids signal propagation issues.
* *8:27** - Clocks and Static Timing Analysis:*
* FPGA signals have a propagation delay. Clocks create "safe zones" for signals to arrive and stabilize, enabling reliable signal processing.
* Static timing analysis calculates these signal paths and timing to ensure stability.
* *13:00** - Registers:*
* Act like small memory units inside the FPGA, storing local copies of signals.
* Used to manage signal propagation delays and provide predictable timing.
* *16:00** - Synchronous vs. Asynchronous Logic:*
* Synchronous: Uses a clock signal for predictable timing (always blocks with a clock).
* Asynchronous: Doesn't use a clock, susceptible to signal timing issues (always blocks without a clock).
* *18:40** - Inferred Latches & How to Avoid Them:*
* Inferred latches are problematic, unintended memory elements caused by feedback loops in asynchronous logic.
* They occur when:
* A signal drives itself within an asynchronous always block.
* Default cases or missing cases in case statements within asynchronous logic.
* To avoid latches:
* Use registers to introduce clocks in loopback paths.
* Define all possible signal behavior conditions in asynchronous always blocks and case statements.
* *27:05** - Summary*
* *28:56** - Outro*

The video concludes by emphasizing the importance of understanding these fundamentals for reliable and efficient FPGA design.


i used gemini 1.5 pro

[jaoblx]

I am happy to see you again here! Can you please do a video about PCIe with ultrascale+

[anonymouscommentator]

loved the video, thank you very much 😊

[kortaffel]

Greetings mysterious woman. Long time no see!~

Welcome back <3

[olaoluwaraji]

Great video.

Which software or tool did you use to draw your logic and timing diagrams?

Thanks

[cccmmm]

Great to see another one.
If you are going to use a system Verilog types is there a reason you don't also use always_ff?

[stevenh]

Thank you for your videos, which have been of great benefit to me (a master's student trying to learn FPGA and ASIC on my own). I would like to ask if I want to learn FPGA as a career choice. Do I need to learn ASIC-related subjects in advance as a foundation? (Such as understanding the underlying principles of pll and so on)

[vijay_]

1.When you have separated the original state_counter logic from the always block you said those are functionally equal .But this is not always correct .The key thing is you should not use reset signal for the combinational circuits .It will cause metastable issues during reset de-assertion case .It is also not a good coding practice.
2.There are three kinds of circuits in digital design combinational, synchronous sequential and asynchronous sequential. once you have changed state_counter in the assign statement to state_counter_new, the assign statement logic circuit is no more asynchronous and it becomes combinational
3.The second image at 19:30 is not clear. You should have used arrow for the feedback path and reverse the latch element connections

[bju]

Hi... Can you made video on some algo implementation on vivado

[ivangecov]

Have you ever thought about being an analog engineer ? At some point is it boring being a digital designer/verificatio engineer ? You are doing the same thing over and over again ?