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CppCon 2016: “Instruction Re-ordering Everywhere: The C++ 'As-If' Rule and the Role of Sequence'
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This is an introductory (i.e., "First Principles") dive into instruction re-ordering (at compile-time, and at run-time) due to conspiring by the compiler and CPU to make most efficient use of execution units and resources within the CPU processor core. Discussion is made of the role for sequence, for tracing of data flows and control flows, how "out-of-order" execution occurs within the compiler and CPU, and why that's a "good thing". The importance of the C++ "As-If" rule that allows these optimizations is explained.
Exploration is made of imperative versus sequential devices, physical versus logical sequences, and the role of the CPU cache line. At the end of this talk, it will be obvious for how and why instruction re-ordering occurs, and the programmer's need to consider logical dependencies (and not instruction order) when defining algorithms.
This talk is ideal for any programmer confused after observing instruction reordering in their running systems, and provides a solid basis to begin reasoning about how to leverage parallelism and be concerned with concurrency.
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Charles Bay
Senior Software Engineer, F5 Networks
Software developer with 25+ years experience in large-scale and distributed systems in performance-sensitive environments including real-time processing, performance visualization, embedded systems, time-sensitive processing of large data sets, hardware status-and-control, and instrument/process/sub-assembly monitoring.
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This is an introductory (i.e., "First Principles") dive into instruction re-ordering (at compile-time, and at run-time) due to conspiring by the compiler and CPU to make most efficient use of execution units and resources within the CPU processor core. Discussion is made of the role for sequence, for tracing of data flows and control flows, how "out-of-order" execution occurs within the compiler and CPU, and why that's a "good thing". The importance of the C++ "As-If" rule that allows these optimizations is explained.
Exploration is made of imperative versus sequential devices, physical versus logical sequences, and the role of the CPU cache line. At the end of this talk, it will be obvious for how and why instruction re-ordering occurs, and the programmer's need to consider logical dependencies (and not instruction order) when defining algorithms.
This talk is ideal for any programmer confused after observing instruction reordering in their running systems, and provides a solid basis to begin reasoning about how to leverage parallelism and be concerned with concurrency.
—
Charles Bay
Senior Software Engineer, F5 Networks
Software developer with 25+ years experience in large-scale and distributed systems in performance-sensitive environments including real-time processing, performance visualization, embedded systems, time-sensitive processing of large data sets, hardware status-and-control, and instrument/process/sub-assembly monitoring.
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