How to write SPI Interface code in Verilog HDL for a 12-bit ADC (using the DE0-Nano)

Writing SPI interface code for ADCs is all about getting the timing right. In this video, I go through, step by step, my process for writing SPI interface code in Verilog. I'm using the DE0-Nano FPGA development board with its on-board ADC128S022 - a 12-bit, 8-channel 200 ksps ADC. This video also serves as a good tutorial on the use of Signaltap for debugging FPGA signals in real time.

00:00- Introduction
00:49 - SPI Overview
2:38 - Looking at the datasheet for the ADC128S022
7:43 - Verilog code
14:21 - Simulation
26:19 - BDF development and programming the device

[vevasam]

Just 35 seconds into your video and I already subscribed. You have a very pleasant voice and pace, and a clear way of explaining. Thank you for your efforts.

[vivek_adi]

It's really an exhaustive explanation of the SPI interface for peripherals to the Cyclone IV.
Keep making them, Awesome !!

[moinkhan-xdpe]

Thankyu sir ... waiting for your more videos on different topic of FPGA

[RickMacmurchie]

I had to watch this a bunch of times but I got a version to work, with indentation and longer more descriptive variable names. One thing that had me stumped me for a bit was that the PLL setup just crashed every time I tried to run it. I ended up writing a simple clock divider module to divide the 50MHz clock down to 3.2 MHz, it happens to be integer divisible, so the PLL is really overkill when synchronization is not needed. Thanks for the detailed tutorial a learned a bunch trying to get this to work.

[ahmedaksu]

Thanks for this great video! There's just one thing. I think count on line 82 (44:39) will never get into case 16 since it is a 4bit register.

[autumnfox]

Thank you for the amazing material!
What kind of BNC adapter/setup are you using to connect the Function Generator's output to the de0-nano PMOD?
Also, would you recommend getting de0-nano or de10-nano?

[noniusreccaredus]

If I understood well (in minute 35), you are sending by 'din' the channel address 3'b 010 (=2) but 'dout' in the analyzer is the result of sampling Channel 0 ??

[shivaramakrishna]

How can you use intial begin for spi_interface design code ( it will not get synthized?)

[polamounika]

Sir can I use this code for DE10LITE in quartus prime FPGA?

[saikumargade]

design and implemntation of spi protocal using veilog Hdl is this board or other board is avilable sir

[wingermathieu]

Hello Sir, thanks a lot for this excellent video ! 😁 I work on the DE0-Nano board and I am trying to add the multiplexing of the 8 channels of the ADC to your code. But it doesn't work ! Can I send you my project files so that you can correct it ?

[muhammadkashif]

Why do you not take timings in your consideration mentioned in timing diagram

[jimmi_jimmi]

hello sir and congratulations on your great video. I try to implement an spi for cyclone ii but it doesnt work right and i am desperate for help. Could I email you for further questions?

[scor]

Pls use some code formatting. That cs?1:clk blow my mind

[Raviteja-cqmb]

what if we want to operate in three channels, how do we proceed with the code?

[Martini_GP]

can you please add the codes in the video description?

[mayanksinghania]

Can you please show the connection you did on the board.

[anshumansingh]

Thank you so much...can u plz provide the code??

[CloudDevOps_raj]

hello sir where can learn verilog for perfect implementtion

[sarathchandra]

I used the same `timescale command but it is not working