Fixed vs Variable Length Instructions

Computer CPU's may use instruction sets that have either a fixed or variable length of instructions. Variable-length instructions require multi-step fetch and decode, but allow for a much more flexible and compact instruction set.
Fixed-length instructions allow easy fetch and decode, and simplify pipelining and parallelism. They do however require more memory as some instructions will be larger than required (Halt or Break for example may require no operands, but would have to occupy the same memory as instructions that do).

In addition, this video explorer which types of processors commonly use fixed and variable length instructions.

If you have not seen the Little Man Computer (LMC) series of videos, they are highly recommended before this one you can find them here:

[JacksonBenete]

What about an architecture where the first bits of the word hint a specific "fixed" length instruction, so we can have some variations but also keeping it "fixed" on some options to reduce the complexity of decoding the instructions?

We could use two bits to have 2, 4, 8, 16 sizes...
00 - 2 bytes long instruction
01 - 4 bytes (standard word?)
10 - 8 bytes
11 - 16 bytes

While this is not as flexible as a variable length to use a 5~7 bytes instruction, it's either 4 or 8, we could still have some variation but being "flagged" up ahead wouldn't be as complex as a truly variable length to decode.

Why this isn't a good approach?
(I'm assuming it isn't considering it's not being used)

(And maybe it would be in fact 1 byte, 3 bytes, 7 bytes, 15 bytes instructions considering prefixes and other potential "flags" that would take up some bits of our word.