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Understanding the Design of Basic Computer with Common Bus System | Lesson 13 |Computer Organization
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Here we will have Understanding the Design of Basic Computer with Common Bus System.
The basic computer has eight registers, a memory unit, and a control unit.
Paths must be provided to transfer information from
one register to another and between memory and registers. The number of
wires will be excessive if connections are made between the outputs of each
register and the inputs of the other registers.
A more efficient scheme for
transferring information in a system with many registers is to use a common
bus.
The outputs of seven registers and memory are connected to the common
bus. The specific output that is selected for the bus lines at any given time is
determined from the binary value of the selection variables S2, S1, and 50• The
number along each output shows the decimal equivalent of the required binary
selection. For example, the number along the output of DR is 3. The 16-bit
outputs of DR are placed on the bus lines when S2S1S0 = 011 since this is the
binary value of decimal 3. The lines from the common bus are connected to the
inputs of each register and the data inputs of the memory. The particular
register whose LD (load) input is enabled receives the data from the bus during
the next clock pulse transition. The memory receives the contents of the bus
when its write input is activated. The memory places its 16-bit output onto the
bus when the read input is activated and S2S1S0 = 1 1 1 .
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The basic computer has eight registers, a memory unit, and a control unit.
Paths must be provided to transfer information from
one register to another and between memory and registers. The number of
wires will be excessive if connections are made between the outputs of each
register and the inputs of the other registers.
A more efficient scheme for
transferring information in a system with many registers is to use a common
bus.
The outputs of seven registers and memory are connected to the common
bus. The specific output that is selected for the bus lines at any given time is
determined from the binary value of the selection variables S2, S1, and 50• The
number along each output shows the decimal equivalent of the required binary
selection. For example, the number along the output of DR is 3. The 16-bit
outputs of DR are placed on the bus lines when S2S1S0 = 011 since this is the
binary value of decimal 3. The lines from the common bus are connected to the
inputs of each register and the data inputs of the memory. The particular
register whose LD (load) input is enabled receives the data from the bus during
the next clock pulse transition. The memory receives the contents of the bus
when its write input is activated. The memory places its 16-bit output onto the
bus when the read input is activated and S2S1S0 = 1 1 1 .
Link for playlists:
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