Multiplication Algorithm | Signed Magnitude Data || Computer Organization and Architecture

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This video lecture is about the Multiplication Algorithm for Signed Magnitude Data. Multiplication of two fixed point binary number in signed magnitude representation is done with process of successive shift and add operation.

Hardware Implementation for Multiply Operation has been discussed.
Hardware Algorithm for Multiply Operation has also been discussed in detail along with Flow Chart. An example for multiplication is also discussed in detail.

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[dionjohnson]

great thanks maan beautifully explained of really helpful topic

[roshnivishwakarma]

Thankyou so much mam it really helped me!!

[akshatk]

mam please explain with one negative number, if br is negative the we take 2s complement of br, answer is not correct

[amitgangwar]

11:04 Excuse me mam, tell me that SC<----n-1, but in case of numerical u have initially taken 5 bits is SC which is the no. Of bits in multipler but it should be 4 na

[divyaarora]

What is the result of 011101 multiplied by 110101, where both the numbers are signed?

[jhanvigupta]

Could you pls provide it's notes?

[sushobhitjakhmolaAdmin]

question 1:
What does n really mean? is it register size or just the no of bits to represent mutiplier, however taking it any way wont change the answer
Question 2:
assume we B and Q are 8 bit registers, but in this algorithm you are consider all bits of B, which is wrong.
suppose B : 10111011 (-ve number in signed representation) and A : 1001
then we have to ignore the msb of B but it has not been addressed in video
Ques 3: why are we doing Qs:Qs xor Bs

if the number is negative, As should be enough to store its sign

[AtulSharma-krhq]

Ma'am aap next vedio kb upload karengi