how does a Mutex even work? (atoms in the computer??)

Thread synchronization is easier said then done. If you use a library like pthread for multithreading and mutexes, then you're probably going to be okay. But, if you're writing your own RTOS, figuring out how mutexes work under the hood is really important.

Mutexes work under the hood in your OS using atomic operations on the computer processor. Atomic Operations are operations on the CPU that cannot be interrupted and are therefore immune to a race condition.

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[edgeeffect]

I looked at the title and thought "Oh! Everyone knows what a mutex is!" But I'm glad I watched because I'd never thought that acquiring a mutex either needs a mutex or needs to be atomic. ;)
Great stuff as ever!

[Vnifit]

God I love your channel, your videos are the best I've seen on embedded/assembly stuff. Really fascinating topics presented beautifully!

[savithaiyer]

Damn, I’d love a video on a DIY RTOS. Love your videos man!!!!

[KenJackson_US]

If your processor has a Read-Modify-Write instruction, you can implement it in one instruction, simple. If your processor lacks it, the simplest way is to disable interrupts for the read, modify and write instructions and then reenable interrupts. Though you have to be careful to _not_ reenable interrupts if they were initially disabled.

[filker]

This is a good video, though I would have used different instructions for the MuTex.

Most ISAs have instructions that are intended for implementation of synchronization primitives like MutEx and Semaphores. The ARM Cortex-M provides LDREX and STREX. The first sets a reservation for the source memory address. If any other entity writes the location, the reservation is lost. STREX conditionally writes to the location, and will fail if the reservation has been lost. The entity that writes the memory and breaks the lock could be another thread on the same or other processor cores or DMA from an external master. Usually, a MutEx will not be set up in memory that is the target for DMA, but having multiple cores, even on microcontrollers, is becoming more common.

[MindlessMegaLawl]

Mad respect as an argentinian for showing footage of the Super TC2000 motor racing series, one of (if not) the most technologically advanced series in Latin America. Thank you ✨

[jonshouse]

"Mutex in C" should be "Mutex with POSIX threads". Plenty of systems use mutex without pthreads. ESP32 Base code and FreeRTOS for example. Not sure why anyone would make yet another RTOS. FreeRTOS is good for small stuff, NuttX for larger stuff, Linux for big stuff, Any of the three +Gate array for obscure/awkward stuff !

[gaborm]

What are the differences between mutex and semaphore and what are the pros and cons?

[victoraraujo]

I'm a simple man. I see a video of this guy, i watch and leave a like

[luismorales]

Nice, i always wonder how could a mutex gives the security of multithread, the Atomic operations Is the key, thanks Man, AND like

[petevenuti]

what about in distributied systems? are there other techniques that work with highly asymmetric systems? possibly other complete semantics and methodologies that don't require coordination in distributed multi-processor systems. please what can you tell me?

[crustykrist]

great video bro. Very clear and to the point. TY!

[nblamer]

02:29 lock doesn't make instruction atomic; the instructions the prefix has effect are already atomic read-modify-write operations.

SO: "The LOCK prefix ensures that the CPU has exclusive ownership of the appropriate cache line for the duration of the operation, and provides certain additional ordering guarantees. This may be achieved by asserting a bus lock, but the CPU will avoid this where possible."

The effect of lock can be quite dramatic performance drop as "ownership of the appropriate cache line" means that on multi-core architecture the most recent writes into the line have to be propagated to every other core accessing the line (when the cores don't share the caches, the level of sharing varies between architectures and cache hierarchy levels but L1 is typically exclusive).

[Nellak]

Atomic lock sounds like Atomic Clock.

Imagine a processor running on an Atomic Clock using Atomic Locks for Mutexes, while the Program running is running Atomic Simulations that were written in the Atom editor.

[jacob_s]

This just really makes me hate all the assholes on programming forums I had to deal with all the more, back when I first started learning how to program in 2006. Just asking how anything in the standard library works would immediately get you attacked:
"Why are you even asking that; just use the ones in the library"
"What, you think you can do it better"

Even if you managed to get thru to them that you just wanted to learn how they work and weren't trying to implement it yourself, you would suddenly be met with this wall of silence. Always dozens of people willing to criticize, but never anyone willing to actually answer the damn question.

Have learned a lot since then, both about how the underlying mechanics of many programming languages and hardware, as well as that the most vocal people in a group often have little else to contribute that simply being the loudest, but it really made me reluctant to want to deal with other programmers unless it was face to face

[Bvic]

Great video. Now, how does lock work in silicon?

[Meleeman]

this is why global state in frontend apps exists i get it now

[lucidmoses]

May want to add a sleep step in there so your not wasting the cpu. Other threads could be wanting to run.

[whtiequillBj]

I was recently reading about quiescent consistency vs liniarliability.

The document I was reading was: Quiescent Consistency: Defining and Verifying Relaxed Linearizability

tl;dr you wait for all code to end execution (a point of quiescence) so there are no thread collisions.

Linearizability is what you explain with the lock whereas quiescence would be programming the start and end of threads such that they wouldn't collide.
The documentation calls quiescence soft and linearized hard. Cause calls separated by points of quiescence can not collide yet using a lock is used essentially to fake quiescence.

Since you are writing an OS what is it that contributed to using the Linearized paradigm vs using times of quiescence to separator thread timing?

[dominiquefortin]

For my part, I never understood why cpu maker create a “CAS” opcode (compare and set) for mutex. Compare operation require the ALU so are slow as opposed to an “XCHG” opcode (for i86 or TAS for 68k) which is much faster because it is only 1 read and 1 write to memory. From there, you build a spinlock mutex to make an OS mutex which can be used to make a full semaphore.