Все публикации

0:00:46

Boost Readability with Underscores in Numbers : Verilog Coding Hack!

0:02:36

Operations in sensitivity lists !! always @(a && b) .....

0:06:45

Fixded Priority Arbitration | Efficient way to CODE RTL #2 #vlsi

0:03:33

What is the difference between 1 and 1'b1 in Verilog ? || Concatenation Problems { }

0:03:53

What is Reverse Case Statement in Verilog? Case(1'b1)

0:07:15

Strict Priority Arbitration (Design, Testbench, Assertions) CODERTL#1

0:00:59

Universal Chiplet Interconnect (UCIe)

0:06:46

X-propagation in SOC design flow | Do you Love your X !!

0:00:40

what does your phone charger do?

0:00:59

Computers are bad at math !! Floating point

0:00:50

Chip Shortage and why it won’t be ending any time soon #shorts

0:00:20

74 ,54 PREFIXES in CMOS , TTL ?

0:00:37

' I suck at grammar !! ' 'APOSTROPHE' difference ones' complement vs two's complement #shorts

0:03:04

A Google Interview Question. # Digital Design

0:01:00

Asynchronous Clk vs Synchronous Clk # shorts

0:01:00

Distance Vs Difference in Binary #shorts

0:06:48

How to design Clock Divided By 4.5 ? Explained!

0:06:12

Downloading & Installation of Intel Quartus Prime & ModelSim [2022]

0:01:00

Is Multiplexer a Universal Gate?🤔 #shorts

0:04:22

How to swap data of registers using Logic gates? 🤔Brain Teaser #3

0:26:43

What should I learn ,to be good at physical design ? 🤔💭 | A-Z of Physical Design with Nikhil Shah.

0:22:18

In Talk With Expert : NIKHIL SHAH | Part -1 | Will AI Impact VLSI ? 🤔

0:05:05

How to count number of one's in a binary vector using adders?🤔💭 Brain Teaser#2

0:07:21

What is Dual Edge Triggered Flip Flop? How to design it?🤔 Explained 👍