Intel Xeon D's Go-FAST Feature

We take a look at Intel's secret weapon against AMD and Arm. We benchmark Intel Xeon D-2700 series QuickAssist (QAT) accelerators. We also compare it to the AMD EPYC 3000 series. Not only do we have Ice Lake D versus the EPYC 3451, but we also have hands-on numbers with 4th Gen Intel Xeon "Sapphire Rapids" QAT and Milan. Let us get deep into the performance of the latest Xeon D and next-gen Xeons.

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Timestamps
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00:00 Introduction
01:33 Test Setup for QuickAssist
04:19 Intel Xeon D QAT Compression
07:55 IPsec VPN QAT Performance with Xeon D
12:01 nginx HTTPS QAT on Xeon D-2776NT
14:29 4th Gen Intel Xeon Sapphire Rapids QAT
17:56 The "Gotchas" of QuickAssist Technology
21:05 Wrap-up

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Other STH Content Mentioned in this Video
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[JeffGeerling]

At some point people will stop caring about CPU cores, and they'll build out a 5, 000 core chip where there's a core that accelerates every single application that runs on the platform ('Minecraft core', 'ffmpeg core', 'MS Word core', 'Torrent core').

There will just be one CPU core to coordinate all the app cores. Heck, Apple's kind of down that path with how they use like 6 or 8 different specific cores for neural, ISP, prores, etc.

[jfkastner]

Interesting, thank you! Ultimately it all boils down to code - many devs are happy that their creation runs w/o problems - even if you give them the compiler updates for QAT they might not use them, validating code and exchangeability with other platforms will hold them back

[AlexSchendel]

Awesome to see this video! Very excited to see SPR ship!
Also, very minor nit: your TLS throughput graph for perf per thread says QAT hardware at 18T rather than 16T.
I just started working as a firmware engineer at Intel for OpenBMC (feels like I just started but it's been over a year sheesh) and it's definitely exciting to see the platform we worked on getting into the hands of reviewers and customers haha.

[LordApophis]

But where are they, almost a year after the announcement I couldn't find them anywhere.

[NVMDSTEvil]

Epyc 3451 is essentially just a low clocked Threadripper 1950x. There is a Zen 2 variant of the low power Epyc series (7D12, there are retail versions of it), curious why they didnt suggest using it?

Does the motherboard support setting the memory into "channel" or "die" interleave modes? This forces NUMA on the Zen1/1.5 platform which can offer better performance in some applications/operating systems that have trouble controlling NUMA associations by themselves (also Zen 1/1.5 have a bit of an issue on this by themselves so the application/OS is not always at fault). Both modes need to tested as the which one will work best depends on the CPU and memory loadout. For a 1950x for example "channel" is the correct mode, while a 2990wx needs to use "die" mode.

[jaffarbh]

One thing that could be a catch! For any new instructions, virtualisation support is crucial. If the hypervisor doesn’t support the new instructions, or the overhead is too great, this would defeat the purpose. Granted, this isn’t an issue for physical appliances but many appliances these days are virtual.

[JohnAngelmo]

I the Intel QuickAssist Adapter 8970 the latest adapter? And is there any new coming out on the market soon?

[christopherjackson]

I was starting to question the existance of sapphire rapids lol

Good work

[bit-meiko]

the 2% performance deficit is what i saw with my ryzen 1700x back in the day when i was testing with cinebench r15 multithread, in bios setting it my ryzen 1700x as 4+0, or 2+2. 2-3% difference to measure the fabric inpact.

edit: i never really posted on it, cuz i thought it was too little of a margin of error at the time, and was too lazy to do more than 3 runs for each of the 2 config types i did.

[gummy]

1:36 We've come full circle ladies and gents. We're back to the flappy doodles we had on the P4 coolers

[BobHannent]

AMD should be building a response to QAT which is a chiplet that they can place next to the IO Die, even on embedded chipsets. Possibly even a CCD which replaces a normal CPU CCD, perhaps creating an asymmetric design with one CCD focused on performance and the other on acceleration.

[gowinfanless]

Excting!!I expect for the Xeon D2700 for such a long time, and the idea is to make an AI server with dual D2700 +1TB Ram which will be strong enough!

[bad__syntax]

Diggin the new set! The channel growth continues to impress.

[brianpark]

Why no performance number for AMD + QAT external card?

[typeer]

it feels like 10 years from now we're going to have a dedicated accelerator for just about every workload

[emf]

Sounds like these new Intel SR chips with on die QAT will be great for high density front-end web or proxy servers. Will be interesting to see how general performance stacks up with current and next gen Epyc, and if AMD decides to add similar hardware function to io die.

[wskinnyodden]

You realize that these particular EPYC cores are Zen1 or best case scenario Zen1+ right?

[ennio]

Is ISA-L delivering the same compression ratio performance for the large speed increase it delivers purely using software ?

[JasonsLabVideos]

HEY! thats not fair, you changed your shirt to many times in this video :). Good video Patrick !

[jeekie]

Great video! Is it a lot more efficient power wise to use the QAT accelerator vs more cores?