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[Arm DevSummit - Session] Network, DC, HPC SoC Development With Scalable Interconnects and CXL
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Abstract: Developing your own SoC or ASIC containing multiple CPUs, coherent caches, memory, IO, and Accelerators for server, networking, or AI application is no ordinary task. In this session, we will share architectural reference material, models, and tools to help you select an optimal topology to achieve your power, performance, and area objectives with the Arm Neoverse Interconnect.
Presenters: David Koenen, Sr. Product Manager, Arm Inc
Technical Level: Intermediate, Advanced
Target Audience: Architect, Hardware Engineer, Software Developer
Topics: Artificial Intelligence, Industrial, Microcontrollers, SoC Design, Data Centers, Game Development, #HPC, Linaro, Linux, Networking, Performance Analysis, #MachineLearning, #ArmDevSummit
Type: Technical Session
Conference Track: Chip Design Methodology
Air Date: 2020-10-06
Presenters: David Koenen, Sr. Product Manager, Arm Inc
Technical Level: Intermediate, Advanced
Target Audience: Architect, Hardware Engineer, Software Developer
Topics: Artificial Intelligence, Industrial, Microcontrollers, SoC Design, Data Centers, Game Development, #HPC, Linaro, Linux, Networking, Performance Analysis, #MachineLearning, #ArmDevSummit
Type: Technical Session
Conference Track: Chip Design Methodology
Air Date: 2020-10-06
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