VLSI - Lecture 6a: Interconnect (Capacitance)

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Bar-Ilan University 83-313: Digital Integrated Circuits
This is Lecture 6 of the Digital Integrated Circuits (VLSI) course at Bar-Ilan University. In this course, I cover VLSI circuit design, starting with the technology and through the design of complex digital circuits, such as multipliers and memory blocks.

Lecture 6 discusses interconnect and the parasitics associated with the wires not being ideal. Section 6a takes a first general look at interconnect and then describes capacitive parasitics in detail.

Lecture slides can be found on the EnICS Labs web site at:

All rights reserved:
Prof. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University

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I'm engineer in south korea. I admire you, and I really appreciate you beyond belief!

hardware_james

On the coupling waveform slide (20:06), it is stated that Cagg equals Cvictim, but shouldn't it be Cc that equals Cvictim?

dongfreak

This lecture (6a) appears twice on the course playlist

netanellalazar

A good explanation !! Why do inductors are not considered during extraction ? Although mutual inductance could sufficiently alter the current flow in parallel wires.

AbubackerSiddiquehays

I'm a student from India working on this topic. Thanks for the knowledge. But I'm unable to download slides from your faculty page. Can you please resolve that?

spiderman

Can't thank you enough for this course

sss

Hi Sir,

Actually I`m does not understand very well about Coupling Capacitance and Delay. Could you explain to me this point.

زينبالريامية

sir how drivers are affecting the capacitance of a wire ?

akashwayal

Very elaborative video...I have one doubt that if I am modeling single line copper interconnect above ground line then do I have to just consider Cg value or Ctotal value from ptm interconnect model?

takshashilachunarkar

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