Interrupt handling in UVM Test Bench

In this post, we will go over an implementation of interrupt handler logic in UVM Test bench(TB) environment.

In a DUT, typically there will be one or more interrupt pins. Related to interrupts, TB

Would need to check the correctness of interrupts
May need to have routines to service the interrupts
May have mask registers which would need to be checked for correctness.
When there are multiple functionalities in a DUT which trigger interrupt(s), it is better that in the TB, all interrupt related checking and service routine logic are centrally handled.

When there are multiple interrupt pins in a DUT to indicate each individual interrupt, the TB can use the individual interrupt pins in interrupt checkers and to trigger interrupt service routines. When there is a single interrupt pin, there will be a status register which has bits to indicate which particular interrupt status caused the interrupt to assert. In either case, the chip interface can have individual interrupt events for each of the functionality in the DUT and a centralized interrupt handler can take up triggering these individual interrupts which can be used within Test environment by the interrupt checkers and the interrupt service routines.
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